Power-Aware Cache Encryption for Safe Memory State Recovery
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Solution Overview
Problem
Current in-line memory encryption systems with caching capability face performance degradation due to complex cache flush policies and potential data loss during power transitions, lacking configurability and transparency in managing cache states.
Innovation Solution
The implementation of a power-aware cache system (IME-PACS) with autonomous cache flush and state recovery mechanisms, utilizing cryptographic circuitry to encrypt/decrypt cache data during power transitions, and transparently manage cache states through Control and Status Registers (CSRs) and programmable logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache system is added to improve memory access performance, then speed is improved, but device complexity increases due to cache management overhead
Solution Approach 1:
The cache system automatically manages its own state preservation and restoration without external intervention. The control logic monitors power transition signals and autonomously initiates cache flush or preservation operations, eliminating the need for complex external management protocols while maintaining performance benefits
Solution Approach 2:
The system performs cache flush operations before power transitions occur by detecting power transition signals in advance. This preliminary action ensures data is written to memory before power is lost, preventing data loss while maintaining cache performance during normal operation
2Reliability
If cache flush policies are implemented to prevent data loss during power transitions, then reliability is improved, but productivity decreases due to additional latency
Solution Approach 1:
The cache management policy dynamically adapts based on the detected power transition type. For gradual power transitions, the system performs cache flush operations. For sudden power transitions, the system preserves cache state. This dynamic approach ensures reliability when needed while minimizing productivity impact during normal operation
Solution Approach 2:
The system changes the cache management parameter (flush vs. preserve) based on the power transition characteristics. By monitoring power transition signals and adjusting the cache policy parameter accordingly, the system achieves both reliability and productivity optimization without fixed overhead
3Reliability
If cryptographic circuitry is added to encrypt/decrypt cache data during power transitions, then security is improved, but device complexity increases
Solution Approach 1:
The cryptographic circuitry is integrated with the cache control logic into a unified security module. The encryption/decryption functions are combined with the cache management functions, sharing common control signals and data paths. This merging reduces overall device complexity compared to having separate cryptographic and cache management systems
Data Source
AI summary
Technologies for in-line memory encryption with a power-aware cache system (IME-PACS) are described. One memory encryption circuit includes cryptographic circuitry and control circuitry. Control circuitry, in a power-off process, causes the cryptographic circuitry to encrypt the plaintext data of one or more cache entries having the first persistent valid flag set to obtain ciphertext data, and stores the ciphertext data in a memory system. The control circuitry, in a power-on process, loads the ciphertext data from the memory system for the cache entries having the first persistent valid flag set, causes the cryptographic circuitry to decrypt the ciphertext data to obtain the plaintext data, and stores the plaintext data in the one or more cache entries of the first cache.