Cache Memory Error Protection Using Per-Region Bit Error History
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Solution Overview
Problem
Modern computing devices face challenges in reducing power consumption in cache memory while maintaining reliability, as lowering supply voltage increases susceptibility to bit errors due to reduced noise margins, leading to permanent faults.
Innovation Solution
The implementation of history records to dynamically select error protection methods for cache portions, using parity checks and error correction codes only where necessary, and disabling faulty portions to maintain reliability without excessive overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If supply voltage is reduced to lower power consumption, then power consumption decreases, but reliability deteriorates due to increased susceptibility to bit errors
Solution Approach 1:
The patent applies different error protection methods to different portions of the cache based on their error history. Portions with single-bit errors use error correction codes, portions with multi-bit errors are disabled, and portions without errors use standard protection. This localized differentiation allows the system to maintain reliability for affected portions while using minimal protection overhead for the majority of functioning cache portions, enabling lower overall power consumption without sacrificing reliability.
Solution Approach 2:
The cache is divided into multiple portions, each tracked individually through history records. This segmentation allows the system to identify and apply error protection selectively to only those portions that have experienced bit errors, rather than applying protection uniformly across the entire cache. The segmentation enables granular control over where power-consuming protection mechanisms are applied.
2Reliability
If error protection methods are applied to all cache portions, then reliability improves, but protection overhead increases
Solution Approach 1:
Error protection is applied locally only to cache portions that have demonstrated error susceptibility through history records. The system monitors each portion individually and applies error correction codes only to portions with single-bit errors, disables only portions with multi-bit errors, and leaves unaffected portions with standard protection. This localized approach ensures reliability for problematic portions while minimizing protection overhead for the majority of cache that functions normally.
Solution Approach 2:
The patent implements partial error protection by applying error correction mechanisms only to the extent necessary - specifically to cache portions that have experienced bit errors. Rather than applying full error protection uniformly across all cache portions, the system uses partial action by targeting protection only where needed, thereby reducing overall protection overhead while maintaining reliability for affected portions.
3Reliability
If error correction codes are used for all cache portions, then bit error protection improves, but power consumption and complexity increase
Solution Approach 1:
Error correction codes are applied locally only to cache portions that have history records indicating single-bit errors. The system uses history records to identify which portions need error correction and applies ECC only to those specific portions. Portions without error history or with multi-bit errors receive different treatment (standard protection or disablement). This localized application of ECC ensures bit error protection where needed while avoiding the power consumption overhead of applying ECC universally across all cache portions.
Data Source
AI summary
A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.