Cache Error Handling via Replicated Address Storage Avoidance
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Solution Overview
Problem
Data processing systems with cache storage and replicated address storage face challenges in efficiently handling errors, particularly hard errors, which can lead to performance degradation and potential system loops, especially in write back caches and multi-processing systems, where error detection and correction mechanisms are complex and resource-intensive.
Innovation Solution
A data processing apparatus with error detection circuitry that allocates cache record identifiers to a cache location avoid storage upon error detection, preventing further use of erroneous cache records and entries in the replicated address storage, ensuring logical exclusion from the cache storage and maintaining cache coherency without extensive communication overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction techniques are applied to data values read from storage devices, then correct data can be provided to requesting devices, but additional logic is required on the read path which adversely affects timing and power consumption
Solution Approach 1:
The patent divides error handling into separate paths: error detection circuitry independently identifies errors in cache records and replicated address storage entries, while the main read path remains relatively simple. The correction logic is segregated into dedicated error correction circuitry that operates parallel to the normal data path, reducing timing impact on critical paths.
Solution Approach 2:
The patent introduces an intermediary error detection and correction mechanism that sits between the cache storage and the requesting device. This intermediary layer detects errors using ECC (Error Correction Code) and corrects them before data reaches the requesting device, preventing error propagation without requiring complex logic throughout the entire read path.
2Reliability
If corrected data is written back to the same memory location, then the correct data value is stored, but hard errors cannot be corrected by re-writing since the fault in the storage device itself causes the error to recur
Solution Approach 1:
The patent extracts erroneous cache records and replicated address storage entries from active use by identifying them through error detection circuitry. Detected errors trigger invalidation or exclusion of the affected cache lines and address entries, removing them from further processing. This prevents hard errors from recurring by ensuring corrected data is not rewritten to faulty locations.
Solution Approach 2:
The patent performs preliminary error detection and correction before data is written back to storage. Error detection circuitry checks data values and address indications before they are committed to cache or replicated address storage, preventing erroneous data from being stored in the first place. This preliminary validation avoids the need to rewrite corrupted data to the same faulty locations.
3Reliability
If error detection and correction mechanisms are implemented in cache storage and replicated address storage, then system reliability is improved, but the mechanisms become complex and resource-intensive
Solution Approach 1:
The patent merges error detection and correction functionality into the existing cache and replicated address storage structures. Error detection circuitry is integrated with cache controllers and address storage management, sharing existing hardware resources such as comparators, multiplexers, and control logic. This consolidation provides comprehensive error handling without proportionally increasing device complexity.
Solution Approach 2:
The patent implements multi-functional error handling mechanisms that serve multiple purposes: error detection, error correction, cache validity verification, and address storage integrity checking. The same error detection circuitry operates on both cache records and replicated address storage entries, providing universal protection against errors across different storage layers without requiring separate dedicated circuits for each function.
Data Source
AI summary
A data processing apparatus includes processing circuitry, a cache storage, and a replicated address storage having a plurality of entries. On detecting a cache record error, a record of a cache location avoid storage is allocated to store a cache record identifier for the accessed cache record. On detection of an entry error, use of the address indication currently stored in that accessed entry of the replicated address storage is prevented, and a command is issued to the cache location avoid storage. In response, a record of the cache location avoid storage is allocated to store the cache record identifier for the cache record of the cache storage associated with the accessed entry of the replicated address storage. Any cache record whose cache record identifier is stored in the cache location avoid storage is logically excluded from the plurality of cache records.