Cache Eviction Circuitry with Congestion-Aware Data Routing

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Solution Overview

Problem

Current data handling circuitries face inefficiencies in managing cache storage hierarchies, particularly in determining the optimal destination for evicted data items to maintain performance and reduce latency, as they lack effective mechanisms to assess the reusability and congestion levels across different cache levels.

Innovation Solution

The implementation of detector and control circuitry that assesses properties of data items, such as prefetchability and congestion levels, to selectively route evicted data items within a cache hierarchy, ensuring efficient allocation and reducing latency by prioritizing storage in less congested lower cache levels or writing back to memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data items are evicted from cache levels using traditional methods, then cache storage space is freed for new data, but system performance degrades due to increased latency and inefficient use of cache hierarchy

Engineering Contradiction:
Improvedata handling efficiencyVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The detector circuitry performs preliminary assessment of evicted data items before eviction occurs, identifying properties such as reusability and prefetchability in advance. This allows the control circuitry to make informed destination selection decisions, placing data in optimal locations before they are actually needed, thereby reducing future latency and improving data handling efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where detector circuitry continuously monitors properties of data items in the cache hierarchy and provides this information to control circuitry. This feedback loop enables dynamic adjustment of eviction decisions based on actual data characteristics and cache state, optimizing both productivity and minimizing latency through adaptive destination selection

Inventive Principle:
Principle #23Feedback

2Productivity

If detector and control circuitry are added to assess data item properties and select eviction destinations, then data handling efficiency improves, but device complexity increases

Engineering Contradiction:
Improvecache eviction efficiencyVSAvoidcircuitry complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the cache control function into distinct specialized components: detector circuitry for assessing data item properties, control circuitry for making eviction decisions, and routing mechanisms for destination selection. This segmentation allows each component to be optimized independently and simplifies the overall design by dividing complex functionality into manageable, specialized modules

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The detector circuitry is designed to identify multiple properties of data items (reusability, prefetchability, access patterns) using a unified assessment mechanism. The control circuitry uses this multi-faceted information to make comprehensive eviction decisions that optimize overall cache performance, achieving multiple objectives simultaneously without requiring separate specialized circuits for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20230244606A1Circuitry and method
Publication Date: 2023.08.03 ARM LTD
  • US20230244606A1 patent drawing
  • US20230244606A1 patent drawing
  • US20230244606A1 patent drawing

AI summary

Circuitry comprises a memory system to store data items; cache memory storage to store a copy of one or more data items, the cache memory storage comprising a hierarchy of two or more cache levels; detector circuitry to detect at least a property of data items for storage by the cache memory storage; and control circuitry to control eviction, from a given cache level, of a data item stored by the given cache level, the control circuitry being configured to select a destination to store a data item evicted from the given cache level in response to a detection by the detector circuitry.