Cache Eviction Algorithm for Multi-Memory Systems
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Solution Overview
Problem
Existing cache eviction algorithms, such as the LRU algorithm, do not effectively handle systems with multiple memory devices of varying access times, leading to increased average access times and cache misses when data is not appropriately selected for eviction.
Innovation Solution
A method that calculates a product of latency and access frequency ratios for different memory devices and uses this information to select data for eviction, ensuring that data with longer latencies is not retained excessively, thereby optimizing cache ratios and reducing average access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the LRU algorithm is used to select data for eviction from cache memory, then the implementation is simple, but the average access time to main memory increases when multiple memory devices with different access times are used
Solution Approach 1:
The patent changes the eviction selection criterion from purely temporal (LRU) to a composite parameter that includes both access frequency and memory device latency. By calculating an evaluation value that combines these parameters (access frequency × latency), the system adapts the eviction strategy to the specific characteristics of multiple memory devices, thereby reducing average access time while maintaining reasonable implementation complexity.
2Productivity
If data is not appropriately selected for eviction from cache memory, then cache ratios are not optimized, but the system complexity increases with more sophisticated selection algorithms
Solution Approach 1:
The patent optimizes cache ratios by changing the selection parameter from simple recency (LRU) to a composite metric combining access frequency and memory latency. This parameter change enables better cache utilization and optimized cache ratios without requiring complex multi-factor algorithms, achieving a balance between productivity improvement and system complexity.
Data Source
AI summary
An information processing device includes a first memory and a processor configured to receive first data from the second memory, receive second data from the third memory, store the first data and the second data in the first memory, specify a first latency of the second memory and a second latency of the third memory, specify a first access frequency to the second memory, and a second access frequency to the third memory, select one of the first data and the second data based on first value, a second value, a first data volume of the first data, and a second data volume of the second data, the first value being obtained by multiplying the first latency and the first access frequency, and the second value being obtained by multiplying the second latency and the second access frequency, and delete at least a part of data.