Multi-Level Cache Exception Arbitration for Priority Fault Handling
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Solution Overview
Problem
Existing data processor memory systems lack a priority-based exception handling mechanism, leading to non-trivial corrective actions when exceptions occur from lower-priority requestors, such as external masters, and do not effectively manage multiple requests from different masters.
Innovation Solution
An exception priority arbitration unit that prioritizes memory access permission faults and data exception signals based on a fixed hierarchy, where CPU memory access faults take precedence over DMA faults, and non-correctable data exceptions are prioritized over correctable ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If priority-based exception handling is implemented, then exception handling accuracy is improved, but device complexity increases
Solution Approach 1:
The exception handling mechanism is segmented into distinct priority levels (CPU exceptions at highest priority, followed by DMA exceptions, then correctable EDC errors, and finally non-correctable EDC errors at lowest priority). The exception controller is divided into separate detection units for different exception types, each feeding into a priority-based arbitration logic that independently determines handling sequence without requiring complex interconnections between exception sources.
2Productivity
If multiple requests from different masters are serviced simultaneously, then productivity is improved, but reliability deteriorates due to improper exception handling
Solution Approach 1:
The system performs preliminary priority classification of exception sources before executing corrective actions. The exception controller pre-establishes a fixed priority hierarchy that determines the sequence of exception handling, ensuring that critical CPU exceptions are always addressed before less critical DMA or EDC exceptions, even when multiple exceptions occur simultaneously during high-throughput operation.
3Ease of operation
If non-critical exceptions are handled first, then ease of operation is improved, but loss of time occurs due to delayed critical exception handling
Solution Approach 1:
Different exception sources are assigned different priority qualities based on their criticality to system operation. CPU exceptions are assigned the highest priority quality as they directly impact processor functionality, while DMA exceptions receive intermediate priority, and EDC errors receive the lowest priority. This local quality differentiation ensures that time-critical exceptions are handled immediately while maintaining simple arbitration logic.
Data Source
AI summary
This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.