Cache Access Fabric Router Selection

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Solution Overview

Problem

The increasing number of processor cores in servers leads to rising power usage in mesh fabrics that connect processors to cache devices, necessitating a solution to reduce or limit power consumption while maintaining effective cache access.

Innovation Solution

A cache fabric is designed with a first layer of routers and a second layer of clusters of cache controllers, where routers select the appropriate cache controllers based on memory access requests and forward them to the correct cache devices, enabling efficient data retrieval and handling of cache misses through a network of interconnected cache controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a mesh fabric connects increasing numbers of processor cores to cache devices, then cache accessibility and bandwidth are improved, but power usage increases

Engineering Contradiction:
Improvecache access bandwidthVSAvoidpower usage
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The mesh fabric is segmented into multiple domains, each domain containing a subset of router nodes and cache devices. This segmentation allows the fabric to be divided into smaller, independently manageable units that can be activated or deactivated based on workload requirements, reducing overall power consumption while maintaining necessary cache access bandwidth through selective domain activation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Domain router nodes are introduced as intermediary components that manage traffic between different domains and serve as local cache controllers. These domain routers act as mediators that can handle cache access requests locally within a domain, reducing the need for long-distance communications across the entire mesh fabric and enabling more efficient power management through localized control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If a mesh fabric connects increasing numbers of processor cores to cache devices, then cache accessibility is improved, but device complexity increases

Engineering Contradiction:
Improvecache accessibilityVSAvoidfabric complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The mesh fabric is divided into multiple domains with each domain containing a manageable subset of router nodes and cache devices. This segmentation reduces the complexity of individual domain controllers while maintaining overall fabric accessibility, as each domain can be independently managed and configured without affecting the entire system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The fabric architecture introduces a domain dimension overlaying the traditional mesh structure. This adds an organizational layer that groups router nodes and cache devices into domains, providing a hierarchical management approach that simplifies routing and control while preserving the underlying mesh connectivity and accessibility.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20230315642A1Cache access fabric
Publication Date: 2023.10.05 INTEL CORP
  • US20230315642A1 patent drawing
  • US20230315642A1 patent drawing
  • US20230315642A1 patent drawing

AI summary

Examples described herein relate to a cache fabric that includes a first layer of a group of routers and includes a second layer of a plurality of clusters of cache controllers. A router of the group of routers can be accessible via an interface that is to receive a memory access request from a processor and select from a group of cache controllers based on a cluster identifier and memory address and provide the memory access request to the selected group of cache controllers. The selected group of cache controllers can receive the memory access request and service a memory access request from a cache device or forward the memory access request to a second cache controller associated with the cache device or a second cache device.