Cache-Fair Scheduling for Chip Multiprocessors
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Solution Overview
Problem
Conventional scheduling policies for multiprocessors assume a single, indivisible CPU resource, leading to unfair CPU sharing, poor priority enforcement, and inaccurate CPU accounting on chip multiprocessors due to co-runner dependent performance variability, which affects thread performance and billing accuracy.
Innovation Solution
A cache-fair scheduling policy that uses a caching estimator process to determine the fair cache miss rate of threads by measuring actual cache miss rates and applying linear regression to redistribute CPU time, ensuring fair cache sharing without requiring new hardware structures or pre-processing, and is implemented within the operating system to manage CPU resources efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional scheduling policies are used on chip multiprocessors, then CPU time allocation is simplified, but fair CPU sharing deteriorates due to unequal cache sharing among co-running threads
Solution Approach 1:
The patent implements feedback by measuring actual cache miss rates of co-running threads and using this information to dynamically adjust CPU time allocation. The scheduler monitors cache performance metrics and redistributes CPU time to compensate for unequal cache sharing, ensuring that threads receive fair overall CPU access despite hardware-controlled cache allocation biases
Solution Approach 2:
The patent changes the scheduling parameter from fixed time slices to dynamic time allocation based on cache miss rate measurements. By adjusting CPU time quantum as a parameter based on observed cache performance, the system compensates for unequal cache sharing and achieves fair CPU sharing without modifying the underlying cache hardware allocation
2Ease of operation
If threads are granted equal time slices on chip multiprocessors, then CPU time distribution appears equal, but actual forward progress deteriorates due to co-runner dependent performance variability
Solution Approach 1:
The system uses feedback from actual cache miss rate measurements to adjust CPU time allocation. By monitoring the performance impact of co-runners on cache behavior and responding with dynamic time slice adjustments, the scheduler ensures that threads make equal forward progress despite initial equal time allocation appearing fair on the surface
3Device complexity
If conventional CPU accounting is used on chip multiprocessors, then billing calculations are straightforward, but accounting accuracy deteriorates due to varying computation rates with different co-runners
Solution Approach 1:
The patent applies feedback by measuring actual cache miss rates and using this information to adjust CPU accounting. By incorporating cache performance metrics into the accounting mechanism, the system accurately reflects the actual computation accomplished by each thread, ensuring proportional billing that accounts for co-runner dependent performance variability
Data Source
AI summary
A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread concurrently on the chip multiprocessor with a plurality of peer threads to measure the actual cache miss rates of the respective threads while executing concurrently. Additionally, the caching estimator process computes the fair cache miss rate of the thread based on the relationship between the actual miss rate of the thread and the actual miss rates of the plurality of peer threads. As a result, the caching estimator applies the fair cache miss rate of the thread to a scheduling policy of the chip multiprocessor.