Cache Memory Control with FIFO for Throughput Bottlenecks
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Solution Overview
Problem
In environments where data processing throughput is prioritized over cache read latency, existing data processors face a decline in throughput due to the mixing of cache hits and misses, as they cannot process subsequent operations without waiting for responses from upper memory controllers.
Innovation Solution
A data processor design that includes a cache memory control section with a hit/miss determination section, a FIFO storage section, and a cache memory read/write section, which allows for continued processing without waiting for upper memory responses by storing hit/miss determination results and in-block read position information in a FIFO memory, enabling early generation of read commands for cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the data processor waits for upper memory responses before processing subsequent operations, then data processing accuracy is maintained, but data processing throughput deteriorates
Solution Approach 1:
The hit/miss determination section determines whether data is present in the cache memory and generates read commands to the upper memory controller in advance, before the upper memory controller completes its read operation. This preliminary determination allows the data processor to prepare subsequent operations without waiting for the slower upper memory response, thereby improving throughput while maintaining processing accuracy.
Solution Approach 2:
A FIFO storage section is introduced as an intermediary component between the hit/miss determination section and the cache memory control section. The FIFO stores the hit/miss determination results temporarily, allowing the data processor to continue processing operations based on stored determination results while the upper memory operations complete in the background, thus decoupling the processing speed from the memory response time.
2Productivity
If the processor continues operations without waiting for upper memory responses, then throughput is improved, but processing accuracy may deteriorate
Solution Approach 1:
The system implements a feedback mechanism where the FIFO storage section stores the hit/miss determination results and the data processor continuously references these stored results to make subsequent processing decisions. This feedback loop ensures that even though operations proceed without waiting for upper memory responses, the processing accuracy is maintained by consistently using the previously determined cache status information.
Data Source
AI summary
A data processor includes a cache memory control section which includes: a hit/miss determination section which is supplied with a request for data processing to determine whether data to be processed is present in a cache memory and outputs a cache hit/miss determination result and, if having determined that the data is not present in the cache memory, feeds a read command to make an upper memory control section read the data from the upper memory; a FIFO storage which stores the cache hit/miss determination result and the in-block read position information according to a FIFO system; and a cache memory read/write section which reads the hit/miss determination result and the in-block read position information from the FIFO storage and reads the data from the cache memory, or writes the data from the upper memory control section into the cache memory and outputs the data.