Cache Filtering Using DRAM Row Buffer Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional cache mechanisms are inefficient in bridging the speed gap between modern memory systems and processors, particularly in applications lacking spatial and temporal locality, leading to increased cache miss penalties and hardware costs.
Innovation Solution
A cache filtering method that dynamically manages cache by monitoring DRAM open rows, rejecting addresses used once and reducing cache conflicts, thereby reducing cache evictions and transfer times, without requiring additional hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cache mechanisms are used to bridge the speed gap between processor and main memory, then cache performance is improved, but system complexity and hardware costs increase due to larger cache sizes and higher associativity
Solution Approach 1:
The patent segments the cache replacement decision process into two independent components: a filter bank that identifies useful references using row buffer hit information, and a conventional cache that stores data. This segmentation allows the system to achieve better performance without proportionally increasing overall cache complexity, as the filter bank uses simple counters and logic rather than expanding the full cache structure.
Solution Approach 2:
The patent introduces a filter bank as an intermediary component between main memory and the conventional cache. This filter bank uses DRAM row buffer hit signals to identify frequently accessed references and filters them before they reach the cache replacement policy. The intermediary filter bank improves cache effectiveness without requiring the conventional cache itself to become more complex.
2Productivity
If cache size and associativity are increased to improve performance, then more references are kept in cache, but power consumption increases
Solution Approach 1:
The filter bank exploits existing DRAM row buffer hit signals that are already generated during normal memory operations. By using this self-generated information about which rows are frequently accessed, the system can identify useful references without requiring additional sensing circuitry or power-consuming monitoring mechanisms. The filter bank essentially serves itself by repurposing signals that already exist in the memory subsystem.
3Reliability
If hardware is added to keep more references in cache by increasing size or associativity, then cache performance improves, but hardware cost increases
Solution Approach 1:
The filter bank creates a virtual copy of the frequently accessed references identified through row buffer hit signals. Instead of physically duplicating cache structures or adding complex associative arrays, the filter bank maintains simple counters that copy the essential information about which references are useful. This virtual copying approach achieves better reference retention without the hardware cost of physical duplication.
4Loss of time
If pre-fetching schemes are used to fetch data in advance, then some cache misses are hidden, but very long cache miss latencies extending to hundreds of cycles cannot be hidden
Solution Approach 1:
The filter bank performs preliminary identification of useful references by monitoring DRAM row buffer hit signals before cache replacement decisions are made. By proactively identifying which references are frequently accessed and filtering them to the cache, the system prepares useful data in advance, reducing the need for pre-fetching mechanisms and their associated complexities.
Data Source
AI summary
A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.