Cache Flash Write Destination Selection

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing storage devices using flash memory face significant errors and performance degradation after approximately 100,000 erase operations, affecting data processing speed, and there is a need to optimize the selection of write destinations between cache memory and flash memory to enhance data writing speed.

Innovation Solution

A storage device architecture that includes a host interface, cache memory interface, hard disk interface, flash memory interface, command analyzing section, state determining section, and media selecting section to determine the fastest write destination based on write data size and free space, allowing data to be written into either cache memory or flash memory, thereby optimizing data processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is written into flash memory directly, then data writing speed is improved, but the number of erase operations increases causing errors and performance degradation

Engineering Contradiction:

Improvedata writing speedVSAvoidflash memory reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent introduces a buffer memory as an intermediary between the host device and flash memory. Data is first written to the buffer memory which has high write speed, and then selectively transferred to flash memory. This mediator resolves the contradiction by decoupling the direct write path, allowing fast writes to buffer while controlling flash memory erase operations to maintain reliability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The storage system is segmented into two distinct layers: buffer memory and flash memory. Each layer serves a specific function - buffer memory handles high-speed temporary storage while flash memory provides non-volatile persistent storage. This segmentation allows optimization of each layer for its specific purpose, resolving the speed-reliability contradiction.

Inventive Principle:

Principle #1Segmentation

2Speed

If data is written into cache memory, then data writing speed is improved, but the free space in cache memory becomes limited

Engineering Contradiction:

Improvedata writing speedVSAvoidfree space in cache memory

Core Design Contradiction:

SpeedVSQuantity of substance

Solution Approach 1:

The patent implements dynamic write destination selection that adapts based on the current free space in buffer memory. When buffer memory has sufficient free space, data is written there for high speed. When free space is limited, the system dynamically switches to writing directly to flash memory. This dynamic adaptation resolves the contradiction between speed and available space.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the write destination parameter based on buffer memory's free space condition. By monitoring the free space parameter and adjusting the write destination accordingly, the system optimizes between speed (writing to buffer) and space availability (writing to flash when buffer is full).

Inventive Principle:

Principle #35Parameter changes

3Productivity

If the number of erase operations of flash memory becomes large, then data processing capacity increases, but errors occur and performance degrades

Engineering Contradiction:

Improvedata processing capacityVSAvoidflash memory error rate

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism that monitors the number of erase operations on flash memory. When the erase operation count approaches thresholds that could cause degradation, the system receives feedback and adjusts its behavior to reduce further erase operations on vulnerable areas, thereby maintaining reliability while continuing to process data.

Inventive Principle:

Principle #23Feedback

4Productivity

If write destination is selected based on free space only, then cache utilization is improved, but data processing speed is not optimized

Engineering Contradiction:

Improvecache utilizationVSAvoiddata processing speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The patent changes the selection parameters from considering only free space to considering multiple parameters including free space, current write speed requirements, and flash memory erase operation count. This multi-parameter decision-making process optimizes both cache utilization and data processing speed by making informed write destination selections.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7631142B2Method and apparatus for selectively storing data into cache or nonvolatile memory

Publication Date: 2009.12.08 KK TOSHIBA

AI summary

A write medium is selected so as to realize the fastest operation after data including a write command has been received from the host device. A storage device comprises a host interface, a cache memory interface, a hard disk interface, a flash memory interface, a command analyzing section which analyzes the contents of a command inputted from the host interface, a state determining section which determines into which of the cache memory and flash memory data can be written faster based on the relationship between the write data size and the free space of the cache memory if the command analyzed in the command analyzing section is a write command, and a media selecting section which determines a data write destination according to the determination result of the state determining section.