Set Associative Cache Flush Control via Segmented Address Arrays
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Solution Overview
Problem
Existing cache memory apparatuses face challenges in achieving high-speed processing with increased parallelism, leading to increased circuit volume, and struggle to control Set Associative cache memory efficiently, limiting their application.
Innovation Solution
A flush control apparatus that includes a line memory unit to store valid and way information for cache lines, a way specification unit to calculate and search for valid cache lines, and a flush unit to direct the flushing of specific cache lines, enabling efficient control of Set Associative cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the degree of parallelism of address array comparison is increased to achieve high-speed processing, then processing speed is improved, but circuit volume increases
Solution Approach 1:
The patent segments the address array comparison function into two separate units: a flush address array for storing comparison addresses and a tag address array for storing cache line addresses. This segmentation allows parallel comparison operations to be performed without requiring a single large parallel comparison circuit, thereby improving processing speed while controlling circuit volume.
Solution Approach 2:
The patent introduces a new dimensional organization by separating the address storage function (flush address array) from the tag storage function (tag address array). This dimensional separation enables independent optimization of each array's parallelism degree, allowing high-speed processing through the flush address array while maintaining manageable circuit volume through the structured tag address array.
2Reliability
If existing flush control apparatus is used, then data coherency is maintained, but Set Associative cache memory cannot be controlled efficiently
Solution Approach 1:
The patent segments the cache line identification information into two distinct components: valid information (indicating whether a cache line is valid) and way information (identifying the specific way/location of the cache line). This segmentation allows the flush control apparatus to selectively control and invalidate specific cache lines in Set Associative memory structures, enabling efficient control while maintaining data coherency.
Solution Approach 2:
The patent introduces way information as an intermediary element that mediates between the flush address array and the cache memory structure. This intermediary enables precise identification and control of specific cache lines within Set Associative memory, allowing efficient flushing operations while preserving data coherency across multiple processors.
3Device complexity
If flush control is implemented without way information, then circuit complexity is reduced, but specific cache line control becomes impossible
Solution Approach 1:
The patent segments cache line identification into valid information and way information, where way information provides the specific control capability needed for Set Associative memory. This segmentation allows the system to maintain relatively simple circuitry while gaining the adaptability to control specific cache lines, as the way information acts as a compact identifier rather than requiring complex control logic.
Solution Approach 2:
The way information field serves multiple functions: it identifies the specific way/location of a cache line, enables selective flushing of specific cache lines, and works universally across different Set Associative cache configurations. This multi-functionality provides extensive control capability without proportionally increasing circuit complexity.
Data Source
AI summary
A flush control apparatus controls a Set Associative cache memory apparatus. A flush control apparatus includes: a tag memory unit associating a tag identifier identifying a tag which associates a plurality of cache lines and tag information representing whether or not the tag is valid. It also includes a line memory unit, a way specification unit and a flush unit which flushes the way specified by the way specification unit.