Load-Balancing Cache Flushes to Non-Volatile Memory
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Solution Overview
Problem
Existing information handling systems face challenges in efficiently flushing cache data to non-volatile memory, particularly with NVDIMM-P and NVDIMM-F types due to their non-deterministic read/write latencies, making it difficult to estimate and manage power supply requirements during asynchronous DRAM refresh operations.
Innovation Solution
A memory controller is configured to monitor memory input/output traffic, determine the quality of service for each non-volatile memory, and reroute input/output data from a more active memory to a less active one, implementing load-balancing to manage cache flushes effectively during power events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache flush operations are performed to multiple non-volatile memories during power events, then data safety is improved, but power supply complexity increases due to non-deterministic latencies
Solution Approach 1:
The system segments the cache flush operations by directing them to multiple different non-volatile memory devices rather than a single device. This segmentation distributes the power supply load and reduces the impact of non-deterministic latencies from any single memory device, thereby maintaining data safety while reducing power supply complexity.
Solution Approach 2:
The system changes the parameter of cache flush target by dynamically selecting different non-volatile memory devices based on current system state and power availability. This parameter change allows the system to adapt to non-deterministic latencies and optimize power supply requirements during power events.
2Device complexity
If all cache data is flushed to a single non-volatile memory device, then device complexity is reduced, but data loss risk increases during power failures
Solution Approach 1:
The system segments cache data across multiple non-volatile memory devices, so that if one device fails or becomes unavailable during a power event, other devices still contain valid cache data. This segmentation reduces data loss risk while maintaining manageable power supply complexity through distributed operations.
Solution Approach 2:
The system prepares multiple non-volatile memory devices in advance as backup targets for cache flush operations. During normal operation, the system can select from multiple pre-configured memory devices, providing a cushion against data loss if any single device fails during critical power events.
3Reliability
If cache flush operations are performed during normal operation, then data persistence is improved, but memory performance degradation occurs
Solution Approach 1:
The system performs cache flush operations periodically based on power events rather than continuously during normal operation. This periodic action ensures data persistence when needed (during power events) while avoiding continuous performance degradation during normal memory operations.
Solution Approach 2:
The system dynamically adjusts cache flush timing based on system state, performing flushes during power events rather than during normal high-performance operations. This dynamic approach balances data persistence requirements with memory performance optimization.
Data Source
AI summary
An information handling system may include a processor, a memory communicatively coupled to the processor and comprising a plurality of non-volatile memories, and a memory controller. The memory controller may be configured to monitor memory input/output traffic to each of the plurality of non-volatile memories, determine a quality of service associated with each of the plurality of non-volatile memories based on such monitoring, and based on such monitoring and the qualities of service associated with the plurality of non-volatile memories, reroute input/output data associated with a first non-volatile memory of the plurality of non-volatile memories to a second non-volatile memory of the plurality of non-volatile memories.