Network Element Cache Flushing Circuitry for Latency Reduction
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Solution Overview
Problem
In communication networks, the simultaneous updating of cache memories in response to changes in forwarding tables leads to performance bottlenecks and latency issues due to simultaneous accesses by multiple ingress processors, causing packet dropping and performance degradation.
Innovation Solution
Implementing cache-flushing circuitry that de-correlates or dilutes the flushing operations by applying them at a controlled rate or selectively invalidating only affected cache entries, thereby reducing the likelihood of simultaneous accesses to the forwarding table.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memories are updated simultaneously in response to forwarding table changes, then cache consistency is maintained, but performance bottlenecks and latency issues occur due to simultaneous accesses by multiple ingress processors
Solution Approach 1:
The cache flushing operation is segmented into multiple independent updates rather than a single simultaneous update. Each cache memory is flushed independently with different time offsets, dividing the monolithic flushing operation into smaller manageable parts that do not conflict with each other
Solution Approach 2:
The system implements periodic or staggered flushing actions where different cache memories are updated at different time intervals. This periodic action with varying time offsets ensures that cache consistency is eventually achieved while preventing simultaneous access conflicts that would degrade performance
2Reliability
If all cache entries are flushed in response to forwarding table changes, then cache consistency is ensured, but cache misses increase and performance is degraded
Solution Approach 1:
The system extracts and identifies only the specific cache entries that are affected by forwarding table changes, rather than flushing all cache entries. This selective approach removes only the necessary updates from the cache, maintaining consistency for changed data while preserving unchanged entries to avoid unnecessary cache misses
Solution Approach 2:
Different cache memories receive different subsets of updated entries based on their specific needs and the nature of changes. This local quality approach ensures that each cache is updated with precisely the information it requires, optimizing the balance between consistency and performance
Data Source
AI summary
A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.