Hierarchical Cache Flushing via Key ID and Address
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Solution Overview
Problem
Current computer systems lack the capability to manage their hierarchical cache structures in granularity of keys, which is essential for secure and efficient data management, especially with total memory encryption technologies.
Innovation Solution
The proposed solution involves a processor architecture that includes a decoder, a memory ordering buffer, and a first in-core cache module. It utilizes an ISA instruction CFLUSHKEYID to flush specific cache lines in the hierarchical cache structure by matching a designated key identification code and address, enabling key-based management of the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If total memory encryption technology is used to protect confidential data, then system security is improved, but the operating system becomes incapable of managing the hierarchical cache structure in granularity of keys
Solution Approach 1:
The patent segments the cache management function by introducing a dedicated key identification code field in the cache tag structure. This allows the cache to be divided into key-specific segments, enabling the OS to manage different cache portions with different encryption keys independently, thus resolving the contradiction between security and management capability.
Solution Approach 2:
The patent introduces an intermediary mechanism (the key identification code matching logic in the cache controller) that bridges the gap between the encryption system and the cache management system. This intermediary enables key-based cache line identification and flushing without requiring the OS to directly handle encryption keys, maintaining security while enabling granular management.
2Measurement precision
If the hierarchical cache structure is flushed based on key identification code and address, then cache management precision is improved, but the complexity of cache flushing operations increases
Solution Approach 1:
The patent applies preliminary action by pre-storing the key identification code in the cache tag structure along with the address tags. This preliminary organization of data allows the flushing operation to simply compare and match without complex processing, achieving high precision with minimal operational complexity.
Solution Approach 2:
The patent adds another dimension (key identification code dimension) to the traditional cache tag structure. This additional dimension enables precise key-based flushing operations without complicating the existing address matching mechanism, as the key comparison operates independently in parallel with address comparison.
Data Source
AI summary
A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.