Cache Coherency Protocol with Forward State for Multicore Systems
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Solution Overview
Problem
Multicore processor systems face challenges in cache coherency management due to the limitations of existing cache protocols, which often result in inefficient memory bandwidth usage and increased power consumption, particularly when dealing with complex data sharing and communication patterns across cores.
Innovation Solution
Implementing a cache coherency protocol that includes both an 'Owned' and a 'Forward' state, where a cache line is marked as 'F' in the directory, allowing a reader device to receive a copy in an owned state, and requiring the cache with the 'F' state to write the evicted line back to the directory, thereby reducing unnecessary memory bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a cache coherency protocol uses the Owned state (MOESI protocol), then a cache can share a cache line among many caches with exclusive modification rights, but the cache must write the dirty line back to memory upon eviction, consuming memory bandwidth
Solution Approach 1:
The patent introduces a dynamic Forward state that allows cache lines to be shared among multiple caches without requiring write-back to memory upon eviction. The state transitions between Owned, Shared, and Forward states based on access patterns, enabling the system to adaptively optimize for either data sharing or memory bandwidth conservation depending on the specific access scenario
Solution Approach 2:
The patent changes the coherence state parameter from binary (Owned/Shared) to a three-state system (Owned/Shared/Forward). This parameter expansion allows the system to distinguish between cache lines that need write-back protection and those that can be freely shared, thereby reducing unnecessary memory bandwidth consumption while maintaining data integrity
2Speed
If a cache coherency protocol designates one cache to provide cache lines to new readers (MESIF protocol), then memory bandwidth is reduced and access is faster, but the evicted line must be written back to memory, consuming bandwidth
Solution Approach 1:
The patent implements dynamic state transitions where a cache line can move from Forward state to Shared state when evicted, eliminating the need for write-back to memory. This dynamic behavior allows the system to maintain fast cache-to-cache sharing while avoiding unnecessary memory traffic, thereby simultaneously improving speed and reducing energy consumption
3Reliability
If existing cache protocols are used in multicore systems, then basic cache coherency is maintained, but memory bandwidth usage is inefficient and power consumption increases
Solution Approach 1:
The patent extends the traditional four-state (MESI) or five-state (MOESI) coherence protocol by adding a Forward state, creating a six-state protocol. This parameter expansion enables more granular control over cache line sharing and eviction behavior, allowing the system to maintain coherency while reducing unnecessary memory write-back operations and thereby lowering power consumption
Data Source
AI summary
A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.