Cache Group Segmentation for Virtual Memory Address Switching
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Solution Overview
Problem
In virtualized computer systems, address space switches lead to cache invalidation, which slows down execution due to the high indirect cost of revalidating cache entries, as current methods either mark all entries as invalid or perform a page walk for every entry, both of which are inefficient.
Innovation Solution
A method and system that maintain validity of cached mappings by using a cache group with multiple cache elements and a page table tracker array to efficiently manage relationships between guest page tables and cache entries, allowing for selective updating and invalidation of cache entries upon page table modifications, thereby avoiding the need for complete cache regeneration during address space switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all cache entries are marked as invalid during address space switches, then cache consistency is maintained, but execution speed deteriorates due to complete cache regeneration overhead
Solution Approach 1:
The patent segments the cache into multiple independent cache elements, each associated with a specific address space. When an address space switch occurs, only the corresponding cache element needs to be invalidated or updated, rather than the entire cache. This segmentation allows selective maintenance of cache consistency, reducing the overhead from complete cache regeneration while ensuring that each address space's cache remains consistent with its page tables.
Solution Approach 2:
The patent pre-generates multiple cache elements corresponding to different address spaces before switches occur. By having these cache elements prepared in advance, the system can quickly switch between address spaces without performing extensive cache validation or regeneration operations during the switch. This preliminary preparation reduces the execution speed penalty associated with address space switches.
2Reliability
If a page walk is performed for every cache entry during address space switches, then cache validity is ensured, but processing time increases significantly
Solution Approach 1:
Instead of performing a page walk for every cache entry (excessive action), the patent performs page walks only for the specific cache entries that need validation in the current address space (partial action). The system identifies which cache entries are relevant to the active address space and validates only those, rather than universally validating all entries. This partial validation approach ensures cache validity for active entries while minimizing the time loss associated with page walk operations.
3Productivity
If multiple cache elements are maintained for different address spaces, then cache switch efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges multiple cache elements into a unified cache structure that can be selectively activated. Rather than maintaining completely separate cache structures for each address space, the system combines them into a single cache framework with additional metadata or control mechanisms that enable efficient switching between address-specific cache elements. This merging approach maintains cache switch efficiency while reducing the complexity that would arise from fully independent cache structures.
Solution Approach 2:
The cache structure is designed to be universal, serving multiple address spaces through a single multi-functional cache system. The cache elements can be dynamically associated with different address spaces based on the current context, allowing the same physical cache structure to fulfill multiple functions. This universality improves productivity by enabling fast switches between address spaces while avoiding the complexity of maintaining entirely separate dedicated caches for each address space.
Data Source
AI summary
A method is provided for creating and maintaining the validity of a cache group including one or more cache elements. Each of the cache elements corresponds to a different address space in a virtual memory of a computer system. Each of the cache elements include one or more caches that store mappings from virtual addresses to data or values that are functions of or dependent upon physical addresses that correspond to the virtual addresses. When there is an address space switch from a first address space to a second address space, the cache group is searched to find the cache element corresponding to the second address space, and that found cache element is made the current cache element for virtual memory access through the cache element. Changes in the page tables are also detected and reflected in the caches of the cache group to maintain the caches up-to-date.