Cache Hierarchy Hint Mechanism for Exclusive Data Access
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Solution Overview
Problem
In multiprocessor systems, cache coherency issues lead to 'ping-pong' scenarios and false cache sharing, resulting in slower access times and potential data overwriting, especially in systems like NUMA where ensuring exclusive access is challenging, and conventional solutions have drawbacks such as preventing memory pages from being cached or hyper-threading processors sharing caches.
Innovation Solution
Implementing a cache hierarchy hint (CHH) mechanism that determines the cache level attribute for data storage, allowing fine-grained control over cache access by associating CHH bits with virtual or physical addresses, enabling data to be stored at appropriate cache levels to prevent cache thrashing and ensure exclusive access, and dynamically adjusting CHH values based on processor access and importance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cache coherency protocols (e.g., MESI) are used to ensure exclusive access, then data consistency is maintained, but access speed decreases due to additional memory cycles and ping-pong scenarios
Solution Approach 1:
The patent segments the cache address space into multiple regions, each with different coherency policies. Important cache-sensitive data is placed in exclusive regions where a single processor has exclusive access, eliminating coherency protocols for that data. Less important data goes to shared regions where standard coherency protocols apply. This segmentation allows critical data to access cache without the overhead of ping-pong scenarios while maintaining coherency where needed.
Solution Approach 2:
The patent applies different coherency qualities to different parts of the cache address space. Instead of applying a uniform coherency protocol across all cache data, the system assigns local quality attributes (exclusive vs. shared) to specific cache regions based on data importance and access patterns. This allows high-speed exclusive access for critical data while maintaining protocol-based coherency for other data.
2Object-affected harmful factors
If memory pages are prevented from being cached to avoid coherency issues, then access conflicts are reduced, but overall system performance decreases due to loss of caching benefits
Solution Approach 1:
Rather than preventing caching globally or for entire memory pages, the patent applies local quality differentiation to specific regions within the cache address space. Important cache-sensitive data is allocated to exclusive regions where caching is permitted and provides performance benefits without causing coherency conflicts. Other data resides in shared regions with standard caching behavior. This selective approach maintains caching benefits for critical data while avoiding conflicts.
Solution Approach 2:
The patent segments the cache address space into multiple regions with different caching policies. By segmenting rather than uniformly disabling caching, the system preserves caching benefits for data that benefits from it while isolating data that would cause conflicts. This segmentation strategy maintains overall system productivity by keeping fast cache access available for important data.
3Adaptability or versatility
If multiple processors share the same cache level, then resource utilization improves, but false cache sharing and cache thrashing increase
Solution Approach 1:
The patent segments the cache hierarchy into multiple levels with different sharing characteristics. L1 caches remain private to individual processors for fast exclusive access, while L2 and L3 caches provide shared capacity for less time-critical data. This segmentation allows processors to share cache resources at lower levels without causing false cache sharing at the critical L1 level, reducing cache thrashing while maintaining resource utilization benefits.
Solution Approach 2:
The patent introduces a new dimension of cache organization by creating a hierarchical structure with multiple levels rather than a single shared cache. This dimensional change allows the system to provide both exclusive fast access (L1) and shared capacity (L2/L3), resolving the conflict between cache sharing benefits and false cache sharing problems by distributing data across multiple cache dimensions.
4Productivity
If hyper-threading processors share caches, then processor utilization improves, but cache coherence overhead increases even at the closest cache level
Solution Approach 1:
The patent segments the cache address space associated with hyper-threaded processors into exclusive and shared regions. Each hardware thread can be assigned exclusive access to specific cache regions for its critical data, eliminating the need for coherency protocols between threads. Shared regions handle less critical data where standard protocols apply. This segmentation reduces cache control overhead while maintaining high processor utilization.
Data Source
AI summary
A plurality of bits are added to virtual and physical memory addresses to specify the level at which data is stored in a multi-level cache hierarchy. When data is to be written to cache, each cache level determines whether it is permitted to store the data. Storing data at the appropriate cache level addresses the problem of cache thrashing.