Cache History List Segmentation for Concurrent I/O Access
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Solution Overview
Problem
Traditional cache management systems face inefficiencies due to access conflicts and complex updating processes when handling multiple concurrent I/O requests, leading to reduced concurrency and increased response times.
Innovation Solution
The proposed solution involves dividing a single cache history list into multiple lists, allowing each I/O request to be mapped to a specific list, and pre-configuring free cache history lists to enable concurrent access, thereby reducing conflicts and shortening allocation times by obtaining free nodes directly from these lists.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single cache history list is used to track all I/O requests, then comprehensive cache management is achieved, but access conflicts increase and concurrency decreases
Solution Approach 1:
The patent divides a single cache history list into multiple separate cache history lists (e.g., first cache history list, second cache history list, etc.). Each I/O request is directed to a specific list based on mapping rules, which segments the access traffic and reduces conflicts between concurrent requests while maintaining comprehensive tracking capability across all lists.
Solution Approach 2:
The patent introduces a cache manager as an intermediary component that manages multiple cache history lists. The cache manager receives I/O requests, determines which list to use based on mapping relationships, and coordinates access to free nodes across different lists, thereby mediating between the need for comprehensive management and the requirement for high concurrency.
2Device complexity
If a single cache history list is used, then implementation is simple, but access conflicts occur and response time increases
Solution Approach 1:
By segmenting the cache history list into multiple lists, the patent reduces access conflicts and response time. Although the overall structure becomes more complex, each individual list remains simple to manage, and the segmentation enables parallel access that compensates for the increased structural complexity.
Solution Approach 2:
The patent pre-configures free nodes in advance within each cache history list. When an I/O request arrives, the system can immediately allocate pre-prepared free nodes without waiting for dynamic allocation, thereby reducing response time despite the increased number of lists to manage.
3Stability of the object's composition
If concurrent I/O requests access a single cache history list, then centralized management is maintained, but locking prevents true concurrency
Solution Approach 1:
The patent segments the cache history list into multiple independent lists, allowing different I/O requests to access different lists simultaneously without requiring locks on a single centralized structure. This maintains data consistency within each list while enabling true concurrency across multiple lists.
Solution Approach 2:
The patent transitions from a single-dimension centralized cache history list to a multi-dimension structure where multiple parallel lists exist. This dimensional change allows concurrent requests to operate in different dimensions (lists) simultaneously, achieving both consistency within dimensions and concurrency across dimensions.
4Quantity of substance
If free nodes are allocated dynamically without preconfiguration, then memory utilization is optimized, but allocation time increases for concurrent requests
Solution Approach 1:
The patent pre-configures free nodes in advance within each cache history list. This preliminary action ensures that when concurrent I/O requests need to allocate nodes, pre-prepared free nodes are immediately available, dramatically reducing allocation time while maintaining efficient memory utilization through controlled preallocation.
Data Source
AI summary
Embodiments of the present disclosure relate to a method and device for cache management. The method includes: receiving an I/O request associated with a processor kernel; in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists; in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance; and adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists.