Cache Hit-Modified Signal for Memory Access Latency
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Solution Overview
Problem
The increasing disparity in access times between processor cache memories and system memories in computer systems leads to performance issues due to the need for frequent access to system memory, which is time-consuming and bandwidth-intensive.
Innovation Solution
A microprocessor with a cache memory and bus interface unit that asserts a hit-modified signal on the system bus to provide data directly from the cache memory when it holds the data in an exclusive state, thereby avoiding the need for accessing system memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor accesses system memory to retrieve data, then data can be obtained from the system memory, but the access time increases and system performance decreases
Solution Approach 1:
The cache memory pre-stores frequently accessed data from system memory, so when the processor needs data, it can retrieve it from the cache instead of accessing system memory directly. This preliminary action of caching data resolves the contradiction by making frequently used data immediately available, thus improving data access speed while reducing memory access time.
Solution Approach 2:
The cache memory acts as an intermediary between the processor and system memory. When data is requested, the cache memory checks if the data is already stored in its exclusive state, and if so, provides it directly to the processor without requiring system memory access. This intermediary structure resolves the contradiction by eliminating direct system memory access for cached data, thereby improving speed and reducing access time.
2Productivity
If the processor frequently accesses system memory, then all data can be retrieved, but system bandwidth is consumed and performance is degraded
Solution Approach 1:
The cache memory maintains data in its own structure with state information (exclusive, shared, invalid), allowing it to self-determine whether data can be provided without system memory access. When data is in the exclusive state, the cache memory serves requests directly without involving system memory, thus improving system performance while reducing bandwidth consumption. This self-service capability resolves the contradiction by enabling the cache to autonomously handle requests for cached data.
Data Source
AI summary
A microprocessor is configured to communicate with other agents on a system bus and includes a cache memory and a bus interface unit coupled to the cache memory and to the system bus. The bus interface unit receives from another agent coupled to the system bus a transaction to read data from a memory address, determines whether the cache memory is holding the data at the memory address in an exclusive state (or a shared state in certain configurations), and asserts a hit-modified signal on the system bus and provides the data on the system bus to the other agent when the cache memory is holding the data at the memory address in an exclusive state. Thus, the delay of an access to the system memory by the other agent is avoided.