Memory Controller Cache-Hit Resource Reservation to Avoid Retries
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Solution Overview
Problem
Existing memory controller circuit implementations suffer from increased latencies, IC area, and power consumption due to additional buffering when memory access requests need to be retried, as they are returned to network buffers for resubmission.
Innovation Solution
The memory controller circuit design moves the function of current transaction tables and completion buffers to the network interface and retry queue, eliminating the common control portion and integrating arbitration for the tag pipeline within the memory controller, ensuring reserved entries in the retry queue to prevent requests from being returned to the network for resubmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional buffering is added to handle memory access requests that require retry operations, then reliability is improved, but latency increases
Solution Approach 1:
The patent applies preliminary action by reserving retry queue entries before memory access requests are processed. The arbitration circuit reserves entries in the retry queue in advance, ensuring that when a request needs to be retried, the entry is already available. This eliminates the need for additional buffering while maintaining reliability, as the reservation mechanism prevents request loss without requiring extra storage capacity that would increase latency.
2Reliability
If complex resource management is implemented to manage memory access requests, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the resource management function from the arbitration circuit by implementing a separate reservation mechanism. The retry queue entries are reserved independently through a simplified reservation protocol, which separates the complex resource management tasks into discrete, manageable steps. This extraction reduces the overall complexity of the resource management system while maintaining reliable handling of memory access requests.
3Productivity
If retry queue entries are reserved to prevent resubmission, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the reservation mechanism to serve multiple functions simultaneously. The same reservation protocol handles both entry allocation and request tracking, eliminating the need for separate mechanisms. This multi-functionality improves productivity by ensuring smooth request processing while minimizing the added complexity that would result from multiple dedicated systems.
4Loss of time
If external resubmission is eliminated through reserved entries, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent merges the reservation and processing functions into a unified system. The arbitration circuit combines entry reservation with request arbitration, creating a single integrated mechanism that handles both functions. This merging eliminates the need for separate reservation and processing systems, reducing the overall complexity while achieving lower latency through the elimination of external resubmission cycles.
Data Source
AI summary
A memory controller circuit manages access to a memory cache circuit and storage circuits. The memory controller receives a memory access request, and attempts to reserve entries in a first set of storage circuits that are needed to process a cache hit prior to determining whether the memory access request hits in the memory cache circuit. This reservation attempt is performed without attempting to reserve other sets of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss. If the memory controller circuit has successfully reserved entries in all of the first set of storage circuits, processing of the memory access request may be initiated. Conversely, if the memory controller is unable to reserve an entry in at least one of the first set of storage circuits, processing of the memory access request is inhibited.