Cache Hostile Task Segregation for Multi-Core Latency Reduction
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Solution Overview
Problem
In multi-core processing systems, cache hostile tasks that frequently access different memory address ranges cause cache pollution, leading to increased latency for other tasks as data is constantly removed and replaced in shared core caches, disrupting cache access for tasks sharing common memory address ranges.
Innovation Solution
A method to determine and assign cache hostile tasks to dedicated cores, while non-cache hostile tasks are assigned to cores based on their memory access categories, reducing cache latency by minimizing data replacement and maintaining data in closer shared caches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache hostile tasks are assigned to shared cores with other tasks, then core utilization is improved, but cache access latency increases due to cache pollution
Solution Approach 1:
The patent segments cores into two distinct types: cache-hostile cores and non-cache-hostile cores. Cache-hostile tasks are assigned to dedicated cache-hostile cores, while non-cache-hostile tasks are assigned to non-cache-hostile cores. This segmentation prevents cache pollution from affecting tasks that require low-latency cache access, thereby resolving the contradiction between maintaining high core utilization and minimizing cache access latency.
2Adaptability or versatility
If cache hostile tasks access multiple memory address ranges, then task functionality is maintained, but cache replacement frequency increases
Solution Approach 1:
The patent extracts cache-hostile tasks from the general task pool and assigns them to dedicated cache-hostile cores. By isolating these tasks that access multiple memory address ranges, the system maintains their functionality while preventing them from polluting the cache memory used by other tasks. This extraction resolves the contradiction by allowing cache-hostile tasks to maintain their memory access flexibility without degrading the cache hit rate for other tasks.
Data Source
AI summary
Provided are a computer program product, system, and method for determining cores to assign to cache hostile tasks. A computer system has a plurality of cores. Each core is comprised of a plurality of processing units and at least one cache memory shared by the processing units on the core to cache data from a memory. A task is processed to determine one of the cores on which to dispatch the task. A determination is made as to whether the processed task is classified as cache hostile. A task is classified as cache hostile when the task accesses more than a threshold number of memory address ranges in the memory. The processed task is dispatched to at least one of the cores assigned to process cache hostile tasks.