Hierarchical Cache Inclusive State Control via Hit Detection
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Solution Overview
Problem
In multi-core processors with hierarchical cache memory, maintaining data consistency across caches leads to an increase in the number of control circuits and complexity, particularly in vector processors where cache invalidation across multiple addresses is required, exacerbating the complexity of cache control.
Innovation Solution
A processor configuration that includes a hierarchical cache memory with a cache hit determination unit to determine cache hits/misses between higher-order and lower-order caches, allowing the control unit to maintain an inclusive state without the need for explicit invalidation control circuits in the higher-order cache, thereby reducing circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-based cache invalidation control is implemented to maintain data consistency in hierarchical cache memory, then data consistency is maintained, but the number of control circuits increases and complexity increases
Solution Approach 1:
The patent extracts the invalidation control function from the higher-order cache and relocates it to the lower-order cache. The lower-order cache now performs both data storage and invalidation control for the higher-order cache, eliminating the need for separate invalidation control circuits in the higher-order cache while maintaining data consistency.
Solution Approach 2:
The lower-order cache is designed to perform multiple functions: storing data for its own use and simultaneously managing invalidation control for the higher-order cache. This multi-functionality reduces the overall number of control circuits needed in the hierarchical cache system.
2Reliability
If cache invalidation control is implemented for multiple addresses in vector processors, then data consistency is maintained, but control complexity and circuit requirements are significantly increased
Solution Approach 1:
The patent extracts the invalidation control function from the higher-order cache and consolidates it in the lower-order cache. This single location can now handle invalidation for multiple addresses in vector processors without requiring distributed control circuits across multiple cache levels.
Solution Approach 2:
The patent merges the invalidation control functionality into the lower-order cache, combining data storage and invalidation management in a single unit. This consolidation simplifies the control architecture for handling multiple address invalidations in vector processing operations.
3Reliability
If explicit invalidation control circuits are added to higher-order cache to maintain inclusive state, then cache coherence is maintained, but circuit count and control logic increase
Solution Approach 1:
The patent removes the invalidation control circuits from the higher-order cache and relocates this functionality to the lower-order cache. The lower-order cache now independently manages the inclusive state relationship without requiring additional control circuits in the higher-order cache.
Solution Approach 2:
The lower-order cache performs self-service by automatically managing invalidation control for the higher-order cache as part of its normal operation. This self-managed approach maintains the inclusive state without requiring external control circuits or additional complexity in the higher-order cache.
Data Source
AI summary
A processor includes a hierarchical cache memory having a higher-order cache memory and a lower-order cache memory. The hierarchical cache memory is in an inclusive state in which data stored in the higher-order cache memory is included in the lower-order cache memory. The processor also includes a cache hit determination unit configured to determine a cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory at the time of accessing predetermined data, and a control unit configured to perform control to realize the inclusive state, based on the determination results of the cache hit/miss with respect to the higher-order cache memory and the lower-order cache memory.