Cache Architecture with Independent Tag and Data Arrays
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Solution Overview
Problem
Current cache systems with single-ported SRAM devices face performance degradation due to read/write contention, which increases latency and reduces efficiency, especially during cache-hits, as they cannot process read and write operations simultaneously.
Innovation Solution
A cache architecture that includes a tag array, a data array, and a write buffer, where the tag array and data array are accessed independently, allowing for simultaneous read operations and delayed write operations, reducing the need for immediate write completion before processing subsequent requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-ported SRAM devices are used in cache, then device complexity is reduced, but read/write contention increases causing performance degradation
Solution Approach 1:
The cache is segmented into multiple independent arrays: tag array, data array, and write buffer. Each array can be accessed independently, allowing simultaneous read operations on the data array while write operations are buffered separately. This segmentation eliminates read/write contention that would otherwise occur in a single-ported cache structure.
Solution Approach 2:
A write buffer is introduced as an intermediary component between the cache controller and the data array. The write buffer temporarily stores write requests, allowing the cache to process read requests without waiting for write operations to complete. This mediator decouples the timing of read and write operations, eliminating contention.
2Productivity
If simultaneous read and write operations are enabled, then cache throughput increases, but latency increases due to additional buffering
Solution Approach 1:
Write requests are buffered in advance in the write buffer before being executed on the data array. This preliminary buffering allows read operations to proceed immediately without waiting for write completion, improving throughput while managing latency through controlled queuing rather than blocking.
3Productivity
If independent array access is implemented, then read/write contention is reduced, but device complexity increases
Solution Approach 1:
The cache is divided into functionally independent arrays (tag array, data array, write buffer) that can be accessed simultaneously without contention. This segmentation achieves the goal of reducing read/write interference while the modular structure helps manage the inherent complexity through clear separation of concerns.
Data Source
AI summary
A cache is presented. The cache comprises a tag array configured to store one or more tag addresses; a tag control buffer configured to store cache control information; a data array configured to store data acquired from a memory device; and a write buffer configured to store information related to a write request. The tag array is configured to be accessed independently from the tag control buffer, and the data array is configured to be accessed independently from the write buffer.