Processor Cache Index Bits for Trace File Reduction

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Solution Overview

Problem

Current debugging techniques face challenges in managing large trace files, which consume significant storage resources and affect performance, especially when dealing with multiple processing units and related threads.

Innovation Solution

The use of a processor cache with accounting bits, such as index bits, allows for efficient recording of trace files by identifying which processing unit has logged cache values and avoiding unnecessary logging, thereby reducing trace file size and improving scalability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional debugging trace methods are used to record code execution, then complete execution traces can be obtained, but trace file size becomes very large consuming significant storage resources

Engineering Contradiction:

Improvecompleteness of execution traceVSAvoidtrace file size

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential information needed for debugging by recording whether cache lines were modified during execution, rather than recording complete cache state. This selective extraction of critical data (modification status) eliminates redundant information while preserving debugging capability, directly reducing trace file size while maintaining trace completeness

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different recording strategies to different cache lines based on their modification status. Cache lines that were modified are recorded in the trace file, while unmodified cache lines are not recorded. This local differentiation ensures that only relevant execution information is captured, maintaining reliability for modified data while minimizing overall trace size

Inventive Principle:

Principle #3Local quality

2Adaptability or versatility

If trace files are recorded for multiple processing units, then comprehensive multi-thread debugging is enabled, but trace file size and storage requirements increase significantly

Engineering Contradiction:

Improvemulti-processing unit tracing capabilityVSAvoidtotal trace file size

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent merges the tracing functionality across multiple processing units by using a shared cache structure where accounting bits are collectively managed. Related threads share the same cache and accounting mechanism, allowing their execution traces to be recorded in a unified manner. This combining approach enables multi-PU tracing capability while avoiding the exponential growth of separate trace files for each processing unit

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The accounting bits in the cache serve multiple functions: they track modification status for trace recording, identify which processing unit last modified each cache line, and enable related threads to share trace information. This multi-functionality allows a single accounting mechanism to support comprehensive multi-PU debugging without proportionally increasing trace file size

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Loss of information

If all cache line values are logged for every processing unit, then complete debugging information is captured, but storage resources are consumed inefficiently

Engineering Contradiction:

Improvedebugging information completenessVSAvoidstorage resource consumption

Core Design Contradiction:

Loss of informationVSLoss of energy

Solution Approach 1:

The patent extracts only the essential debugging information by recording cache line modification status rather than complete cache line values. The accounting bits capture whether a cache line was modified and by which processing unit, which is sufficient for debugging purposes. This extraction eliminates redundant data storage while preserving all necessary debugging information

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent discards redundant cache line value recordings when the modification status is already captured in the accounting bits. Since the accounting bits track which cache lines were modified and by which processing unit, the actual cache line values do not need to be repeatedly recorded in the trace file, significantly reducing storage consumption while maintaining debugging completeness

Inventive Principle:

Principle #34Discarding and recovering

Data Source

PatentUS11126536B2Facilitating recording a trace file of code execution using index bits in a processor cache

Publication Date: 2021.09.21 MICROSOFT TECHNOLOGY LICENSING LLC

AI summary

Facilitating recording a trace of code execution using a processor cache. A method includes identifying an operation by a processing unit on a line of the cache. Based on identifying the operation, accounting bits for the cache line are set. Setting the accounting bits includes (i) setting the accounting bits to a reserved value when the operation is a write and tracing is disabled, (ii) setting the accounting bits to an index of the processing unit when the operation is a write and the accounting bits for the cache line are set to a value other than the index of the processing unit, or (iii) setting the accounting bits to the index of the processing unit when the operation is a read that is consumed by the processing unit and the accounting bits for the cache line are set to a value other than the index of the processing unit.