Cache Support for Indirect Loads in Graph Applications
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Solution Overview
Problem
Conventional processor architectures face inefficiencies and poor scaling when handling indirect loads and indirect stores, particularly when accessing compressed sparse row (CSR) lists cached sequentially.
Innovation Solution
The implementation of cache support for indirect operations in the Programmable Integrated Unified Memory Architecture (PIUMA) ISA, which includes logic to dereference pointers, cache pointer lists, and generate modified requests for near-memory engines, thereby optimizing performance for graph applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If indirect loads and indirect stores are used for accessing CSR lists, then data manipulation execution time is improved, but performance degrades when the CSR list is cached and sequentially accessed
Solution Approach 1:
The system dynamically switches between indirect and direct access modes based on whether the CSR list is cached or not. When cached, direct sequential access is used; when not cached, indirect access is used. This dynamic adaptation resolves the performance degradation issue by selecting the optimal access method for each scenario.
Solution Approach 2:
The access mode parameter is changed based on cache status. The system monitors whether the CSR list resides in cache and adjusts the access method accordingly - using indirect addressing when the list is in main memory and direct sequential addressing when it is cached, thereby optimizing performance for both cases.
2Device complexity
If conventional processor architecture is used for indirect memory operations, then implementation is simple, but resource usage efficiency is poor and scaling is bad
Solution Approach 1:
The processor architecture is segmented into specialized components for handling indirect operations. Separate logic units are introduced to handle pointer dereferencing, cache lookup, and memory access independently, allowing efficient parallel processing of indirect operations without compromising overall architecture simplicity.
Solution Approach 2:
An intermediary cache structure is introduced between the processor and main memory specifically for CSR lists. This intermediary layer enables efficient sequential access patterns while maintaining the benefits of indirect addressing, resolving the scaling and resource efficiency issues of conventional architectures.
3Length of moving object
If indirect operations are used to access CSR lists, then the number of network hops is reduced, but total latency increases when employing cache memory
Solution Approach 1:
The CSR list is pre-loaded into a dedicated cache structure before indirect operations are performed. This preliminary action ensures that subsequent indirect accesses can be served from the cache without incurring full memory access latency, thereby reducing total latency while maintaining the network hop benefits of indirect addressing.
Solution Approach 2:
A dedicated cache intermediary is positioned between the indirect operation logic and main memory. This intermediary handles the time-consuming cache lookup and data retrieval operations, allowing the indirect operation itself to complete quickly while the intermediary manages the latency-intensive memory access in parallel.
Data Source
AI summary
Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.