Cache Injection Logic with Automatic Locking Mechanism

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Solution Overview

Problem

Conventional data processing systems face performance issues due to premature eviction of cache lines during cache injection operations, leading to increased cache misses and reduced processing efficiency.

Innovation Solution

Implementing 'cache inject and lock' operations to automatically lock injected cache lines in the cache memory, preventing premature eviction and managing cache memory to reserve space for both normal and injected cache lines, with logic to prioritize and manage locked cache lines for efficient use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If cache inject operations are performed to improve processing efficiency, then data access speed is improved, but injected cache lines may be prematurely evicted leading to cache misses

Engineering Contradiction:
Improvedata access speedVSAvoidcache line retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies preliminary action by performing a lock operation immediately when a cache line is injected into the cache memory. This lock is established before any eviction decision is made, ensuring that the injected cache line is protected from premature eviction. The lock is subsequently released only after the processing unit has accessed the cache line, thus preventing the harmful effect of premature eviction while maintaining the speed benefit of cache injection.

Inventive Principle:
Principle #10Preliminary action

2Volume of stationary object

If cache memory storage space is limited, then cache memory size is reduced, but injected cache lines compete with normal cache lines for storage space

Engineering Contradiction:
Improvecache memory sizeVSAvoidprocessing efficiency
Core Design Contradiction:
Volume of stationary objectVSProductivity

Solution Approach 1:

The patent applies local quality by treating injected cache lines differently from normal cache lines through the introduction of a lock mechanism. Locked cache lines (injected lines) are given special protection and are not subject to the same eviction policies as normal cache lines. This local differentiation ensures that injected cache lines retain priority access and are not evicted due to cache full conditions, thereby maintaining processing efficiency without requiring increased cache memory size.

Inventive Principle:
Principle #3Local quality

3Reliability

If cache lines are locked to prevent eviction, then cache line availability is improved, but cache memory management complexity increases

Engineering Contradiction:
Improvecache line availabilityVSAvoidcache memory management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by implementing an automatic lock release mechanism. When the processing unit accesses a locked cache line, the system automatically detects this access and releases the lock without requiring manual intervention. This self-service approach minimizes the management overhead despite the added locking functionality, as the system autonomously handles the lock lifecycle based on actual cache access events.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9176885B2Combined cache inject and lock operation
Publication Date: 2015.11.03 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9176885B2 patent drawing
  • US9176885B2 patent drawing
  • US9176885B2 patent drawing

AI summary

A circuit arrangement and method utilize cache injection logic to perform a cache inject and lock operation to inject a cache line in a cache memory and automatically lock the cache line in the cache memory in parallel with communication of the cache line to a main memory. The cache injection logic may additionally limit the maximum number of locked cache lines that may be stored in the cache memory, e.g., by aborting a cache inject and lock operation, injecting the cache line without locking, or unlocking and/or evicting another cache line in the cache memory.