Opportunistic Cache Injection for Memory Latency Reduction
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Solution Overview
Problem
Current memory management systems face challenges in efficiently managing cache coherence and data access between I/O devices and processors, leading to high latency and inefficiencies in memory access, especially when I/O devices perform direct memory access (DMA) operations.
Innovation Solution
The proposed solution involves a method and apparatus that utilize a tiered memory system with a high latency memory and a low latency memory, where the memory interconnect determines if a cache tag hit occurs in a caching tier closer to the processor, and if so, injects data into that tier, reducing the need for immediate updates in the main memory and minimizing cache pollution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to main memory (DRAM) through traditional memory hierarchy, then data is stored safely, but processor fetch latency increases and power consumption increases
Solution Approach 1:
The patent performs preliminary action by injecting data directly into the L2 cache before the processor needs to fetch it. When an I/O device completes a DMA write, the data is proactively injected into the L2 cache at the memory address where the processor will later read it, eliminating the need for the processor to wait for slow DRAM access. This preliminary placement of data resolves the contradiction by ensuring data is both stored safely (in cache) and readily accessible (low latency) when needed.
Solution Approach 2:
The patent introduces an intermediary mechanism - the memory interconnect with cache injection capability - that mediates between the I/O device and the processor. Instead of direct DRAM access for both DMA writes and processor reads, the interconnect captures DMA write transactions and injects data into the L2 cache, serving as an intelligent intermediary that optimizes the data path. This intermediary resolves the contradiction by creating a fast path for processor reads while maintaining the safety of data storage in the hierarchical memory system.
2Reliability
If data is written to DRAM to ensure storage, then data loss is prevented, but power consumption increases due to full write operations
Solution Approach 1:
The patent applies partial action by performing only the necessary portion of the data transfer - writing data directly to the L2 cache instead of performing a full write to DRAM. Since the L2 cache is part of the memory hierarchy and will manage data placement to DRAM when needed, the system achieves data storage safety with only a partial write operation. This partial action significantly reduces power consumption compared to full DRAM writes while maintaining reliability through the cache hierarchy's data management mechanisms.
3Productivity
If I/O devices perform direct memory access to DRAM, then data transfer is efficient, but cache coherence and data access efficiency deteriorate
Solution Approach 1:
The patent merges the I/O data transfer path with the processor cache hierarchy by enabling direct injection of I/O data into the L2 cache. Instead of separate paths for I/O DMA transfers and processor memory access, the system combines them through the cache injection mechanism. The memory interconnect monitors I/O write transactions and automatically injects data into appropriate L2 cache lines, merging the previously separate I/O and processor memory paths. This merging maintains data transfer efficiency while simplifying cache coherence management, as the cache hierarchy naturally handles coherence through its existing protocols.
4Speed
If data is placed in low latency cache, then processor access speed improves, but cache pollution increases
Solution Approach 1:
The patent applies local quality by making the cache injection targeted and selective rather than universal. The memory interconnect analyzes I/O write transactions and injects data only into specific L2 cache lines corresponding to addresses where the processor is likely to read the data. This targeted approach ensures that useful data is placed in the cache without filling it with irrelevant or polluting data. The local quality principle resolves the contradiction by ensuring fast processor access to needed data while preventing cache pollution through selective, address-specific injection decisions.
Data Source
AI summary
According to one general aspect, a method may include receiving a request, from a non-central processor device that is configured to perform a direct memory access, to write data within a memory system at a memory address. The method may also include determining if a cache tag hit is generated, based upon the memory address, by a caching tier of the memory system that is closer, latency-wise, to a central processor than a coherent memory interconnect. The method may further include if the caching tier generated the cache tag hit, injecting the data into the caching tier.