Cache Data Integrity Bits for Fast Single-Bit Error Correction
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Solution Overview
Problem
Existing data validation and correction mechanisms in microprocessor caches are inefficient, leading to delays due to the need for reloading duplicate data from lower-level caches to correct errors, which can be caused by environmental radiation or intentional tampering.
Innovation Solution
Implementing a data validation method using a combination of single-bit error correcting (SEC) code bits and parity bits to quickly identify and correct single-bit errors in cache data, ensuring data integrity by associating each data item with a unique coding pattern and generating integrity bits for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duplicate data are stored in lower-level cache or external memory to correct errors, then data reliability is improved, but processing time increases due to reloading delays
Solution Approach 1:
The patent applies preliminary action by pre-computing and storing syndrome bits (SEC and parity bits) alongside data in the cache during the write operation. When data is read, these pre-stored syndrome bits enable immediate error detection and correction without needing to reload from lower-level memory, thus resolving the time delay while maintaining reliability
2Reliability
If error detection and correction mechanisms are implemented in cache, then data reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the error correction code into two distinct parts: SEC (single-error correction) bits and parity bits. This segmentation allows the system to handle different types of errors with appropriate methods - SEC bits for single-bit errors and parity bits for detection - simplifying the overall decoding logic while maintaining robust error correction capability
Solution Approach 2:
The patent applies local quality by using different coding strategies for different portions of the data. SEC bits are used for locations where single-bit errors are most likely to occur, while parity bits provide additional detection capability. This localized approach optimizes error correction efficiency without requiring complex universal correction mechanisms
3Productivity
If hybrid parity and error correcting codes are used for error detection and correction, then productivity is improved by avoiding reload delays, but device complexity increases due to additional integrity bits
Solution Approach 1:
The patent merges the error detection and correction functions into a unified hybrid code structure where SEC bits and parity bits work together. This combination allows the system to detect and correct errors within the cache using a single integrated mechanism rather than separate systems, improving productivity while managing complexity through functional integration
Data Source
AI summary
This application is directed to protecting a data item by storing data bits with integrity bits. The data bits are assigned into a second number of data sets. Data bits of each data set are combined to determine a third number of respective coding bits based on a respective coding pattern. The integrity bits include a set of single-bit error correcting (SEC) code bits and a set of parity bits. Each SEC code bit is a combination of a respective bit of the third number of respective coding bits of each of the second number of data sets, and each parity bit is a combination of a respective subset of SEC code bits and data bits in a respective one of the second number of data sets. These integrity bits are stored with the first number of data bits in a memory for protecting the data item.