Cache Interconnect Congestion Controller for Clean Write-Back Blocking
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Solution Overview
Problem
In multi-core processing systems, clean write backs from higher level caches to lower level caches can cause congestion on the interconnect, reducing system performance by occupying bandwidth and exacerbating interconnect congestion.
Innovation Solution
A congestion controller is used to dynamically block transactions that involve writing back clean data from higher level caches to lower level caches, minimizing congestion by intercepting and eliminating these transactions before they reach the interconnect, and proxying responses to maintain system functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clean data is written back from higher level caches to lower level caches, then data coherency is maintained, but interconnect congestion increases and system performance decreases
Solution Approach 1:
The patent extracts and eliminates unnecessary clean write-back transactions from the cache hierarchy. The congestion controller identifies and blocks clean write-back transactions before they enter the interconnect, removing the harmful traffic component while preserving essential cache operations. This extraction approach maintains data coherency for modified data while eliminating congestion-causing clean data transfers.
Solution Approach 2:
The congestion controller acts as an intermediary component between the higher level cache and lower level cache. It intercepts write-back transactions, determines whether they are clean or dirty, and selectively blocks clean transactions while allowing dirty transactions to proceed. This intermediary mechanism resolves the contradiction by filtering traffic at the source without disrupting the overall cache coherency protocol.
2Adaptability or versatility
If clean write back transactions are allowed on the interconnect, then cache hierarchy functionality is maintained, but bandwidth availability decreases during peak usage
Solution Approach 1:
The congestion controller dynamically adjusts traffic flow based on real-time interconnect conditions and transaction characteristics. It continuously monitors write-back transactions and adaptively blocks clean transactions while permitting dirty transactions, creating a dynamic traffic management system that optimizes bandwidth utilization without compromising cache hierarchy functionality.
Solution Approach 2:
The patent applies different quality treatment to different types of cache transactions. Clean write-back transactions are blocked at the congestion controller, while dirty write-back transactions are allowed to proceed to the lower level cache. This local quality differentiation ensures that only necessary data transfers consume bandwidth, preserving bandwidth availability for peak usage periods.
3Productivity
If all write back transactions are blocked, then interconnect congestion is reduced, but data coherency is compromised
Solution Approach 1:
The congestion controller changes the blocking parameter based on the dirty/clean status of the cache data. Instead of uniformly blocking all write-back transactions, it uses the dirty bit status as a parameter to selectively block only clean transactions while allowing dirty transactions to proceed. This parameter-based differentiation maintains data coherency while achieving congestion reduction.
Solution Approach 2:
The patent segments the write-back transaction stream into two distinct categories: clean transactions and dirty transactions. The congestion controller processes these segments differently, blocking clean segments while permitting dirty segments to flow through the interconnect. This segmentation approach ensures that data coherency is maintained for modified data while eliminating unnecessary traffic from clean data.
Data Source
AI summary
A congestion controller may be configured to control traffic on an interconnect between a higher level cache and a lower level cache. The lower level cache may also be coupled to a main memory. The congestion controller may be configured to reduce congestion on the interconnect by blocking transactions that include writing of data to the lower level cache if the data has not been modified relative to a copy of the data in the main memory. The congestion controller may also be configured to control the traffic by blocking certain transactions in a controlled manner for traffic shaping or for performance features.