Cache Access Circuit With Configurable Address-Interval Hit Detection
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Solution Overview
Problem
Existing data processing systems face inefficiencies due to limited cache storage space and the inability to directly access cache data, leading to time penalties and reduced elasticity in data retrieval, especially when using tightly coupled memories with fixed address intervals.
Innovation Solution
A data processing apparatus with a memory circuit and data accessing circuit that determines cache hits or misses based on address tags and predetermined intervals, allowing for flexible operation between cache memory and tightly coupled memory modes, optimizing data retrieval and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache storage space is increased to store more data, then data retrieval efficiency is improved, but storage space limitation causes important data to be evicted to main memory resulting in time penalty
Solution Approach 1:
The patent merges the cache memory and tightly coupled memory into a single unified memory structure. This allows the system to simultaneously provide the fast access characteristics of cache and the large storage capacity of tightly coupled memory, eliminating the need to evict important data to main memory and avoiding the associated time penalties.
Solution Approach 2:
The unified memory structure serves multiple functions: it operates as a cache for frequently accessed data and as a tightly coupled memory for important data that requires persistent storage. This multi-functionality allows the system to improve data retrieval efficiency while maintaining adequate storage space without requiring separate memory structures.
2Reliability
If tightly coupled memory is used with fixed address intervals to avoid data replacement, then data retrieval stability is improved, but elasticity of use is reduced
Solution Approach 1:
The patent introduces dynamic configurability to the memory structure, allowing the address interval configuration to be adjusted based on different operational requirements. The memory can be configured with different address interval settings through control signals, enabling the system to adapt between fixed interval mode (for stability) and flexible interval mode (for elasticity) as needed.
Solution Approach 2:
The patent changes the parameter of address interval configuration from fixed to variable. By introducing control signals that can modify the address interval parameters dynamically, the system maintains data retrieval stability when fixed intervals are needed while also providing elasticity when address intervals need to be adjusted for different access patterns.
3Productivity
If cache addresses are made unknown to user for automatic management, then data retrieval efficiency is improved, but direct access capability for observation is lost
Solution Approach 1:
The unified memory structure acts as an intermediary between the processor and main memory, providing automatic cache management while still allowing user access to data. The memory management unit handles automatic caching operations to maintain efficiency, while the unified structure permits controlled direct access for observation purposes, bridging the gap between automatic management and user accessibility.
Data Source
AI summary
A data processing apparatus including a memory circuit and a data accessing circuit is provided, in which the memory circuit includes multiple cache ways configured to store data. In response to a first logic state of an enabling signal, if a tag of an address of an access requirement is the same as a corresponding tag of the multiple cache ways, the data accessing circuit determines that a cache hit occurs. In response to a second logic state of the enabling signal, if the address is within one or more predetermined address intervals specified by the data accessing circuit, the data accessing circuit determines that the cache hit occurs, and if the address is outside the one or more predetermined address intervals, the data accessing circuit determines that a cache miss occurs.