Multicore Cache Invalidation via Narrower Packet Sequences
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Solution Overview
Problem
As the number of processor cores increases, the complexity and cost of communicating cache invalidation information between lower-level and higher-level caches in multicore processors grow, due to the need to convey detailed invalidation information for each core, leading to increased die area and power consumption.
Innovation Solution
The implementation of a processor architecture that conveys invalidation information through a sequence of narrower invalidation packets, each corresponding to a respective higher-level cache line, rather than conveying all information concurrently, allowing for efficient communication of invalidation data across multiple cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If all invalidation information for multiple higher-level cache lines is conveyed concurrently through a wide interface, then the invalidation process is completed faster, but the interface bandwidth and implementation costs increase
Solution Approach 1:
The patent segments the invalidation information into multiple separate invalidation packets, each corresponding to a specific higher-level cache line. Instead of transmitting all invalidation information simultaneously through a wide interface, the system transmits multiple narrower packets sequentially. This segmentation reduces the required interface bandwidth while still achieving complete invalidation of all affected cache lines, resolving the contradiction between interface complexity and invalidation completeness.
2Use of energy by stationary object
If a narrower interface is used to convey invalidation packets, then the implementation costs and power consumption are reduced, but the invalidation process takes longer
Solution Approach 1:
The patent divides the invalidation information into multiple packets transmitted through a narrower interface, reducing power consumption compared to a wide interface. The sequential transmission of these packets accepts increased latency as a trade-off for reduced power consumption and implementation costs, directly addressing the contradiction between energy efficiency and speed.
3Reliability
If detailed invalidation information is communicated for each processor core, then cache coherence is maintained accurately, but the complexity of routing and implementation costs increase
Solution Approach 1:
The patent segments invalidation information into individual packets, each targeting a specific higher-level cache line and containing only the necessary information for that particular cache line. This segmentation allows the routing logic to handle simpler, more targeted information rather than complex comprehensive invalidation data, reducing routing complexity while maintaining accurate cache coherence through precise delivery of relevant invalidation information to each core.
Data Source
AI summary
A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.