Multi-core Cache Invalidation Tags for Latency Reduction
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Solution Overview
Problem
Cache coherence policies in multi-core systems face performance delays due to the need for arbitration of invalidation commands, which can lead to latency issues, especially in systems with shared caches and write-through policies.
Innovation Solution
The implementation of invalidation tags that manage and process invalidation commands separately from cache tag arrays, reducing bandwidth and power requirements, and employing a Bloom Filter-like structure to minimize spurious invalidations by hashing and tracking received commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If invalidation commands are processed through arbitration with other cache commands, then cache coherence is maintained, but processing latency increases
Solution Approach 1:
The patent segments the cache tag structure into two independent parts: traditional cache tags for data address matching and separate invalidation tags for storing invalidation command information. This segmentation allows invalidation commands to be processed independently from other cache commands, eliminating arbitration delays while maintaining cache coherence through separate invalidation flag updates.
2Reliability
If write-through policy is implemented to eliminate dirty data, then data consistency is improved, but performance deteriorates
Solution Approach 1:
The patent introduces invalidation tags as an intermediary structure that stores invalidation command information separately from the main cache operation path. This intermediary allows the system to maintain dirty data in caches without immediate write-back to main memory, while still ensuring data consistency through separate invalidation processing that updates invalidation flags based on the stored invalidation commands.
3Reliability
If multiple invalidation commands are received simultaneously, then cache coherence is maintained, but command processing delay increases
Solution Approach 1:
The patent implements preliminary action by pre-storing invalidation command information in separate invalidation tags before actual cache access occurs. When invalidation commands are received, their information is immediately recorded in the invalidation tags without requiring arbitration with other commands. The actual invalidation flag updates are then performed based on this pre-stored information, eliminating processing delays while maintaining coherence.
Data Source
AI summary
A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.