Cache Invalidation Unit for DMA Coherence
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Solution Overview
Problem
In computing systems with caches and alternate bus masters, cache and main memory incoherency issues arise due to DMA writes, leading to complexity, increased load on the processor, and high power consumption in bus snooping solutions, which are error-prone and difficult to debug, especially in embedded applications like vision processing.
Innovation Solution
A cache invalidation unit is introduced to prevent incoherence by generating invalidation requests based on preconfigured memory regions and transferring them to the cache memory, ensuring that outdated copies are invalidated, thereby maintaining coherence between cache and main memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus snooping is implemented to handle cache-main memory incoherency, then cache coherence is maintained, but device complexity and power consumption increase significantly
Solution Approach 1:
The patent extracts the cache invalidation function from the complex bus snooping mechanism and implements it as a separate, dedicated cache invalidation unit. This unit independently monitors DMA write operations and generates invalidation requests without requiring full bus snooping logic, thereby reducing overall system complexity while maintaining coherence.
Solution Approach 2:
The cache invalidation unit acts as an intermediary component between the DMA controller and the cache memory. It receives information about DMA write operations and translates this into appropriate cache invalidation requests, mediating the interaction between these two components without requiring them to directly implement complex snooping logic.
2Reliability
If bus snooping is used to maintain cache coherence, then data consistency is ensured, but power consumption increases
Solution Approach 1:
The patent extracts only the essential invalidation monitoring function from the power-consuming bus snooping mechanism. The cache invalidation unit selectively monitors only the memory addresses affected by DMA operations and generates invalidation requests only when necessary, avoiding the continuous monitoring and high power consumption of full bus snooping.
Solution Approach 2:
Instead of continuous monitoring characteristic of bus snooping, the cache invalidation unit operates periodically or event-driven based on DMA write operations. It is triggered only when a DMA write occurs to a memory address that corresponds to cached data, thereby reducing power consumption while maintaining data consistency.
3Reliability
If cache PUSH and INVALIDATE instructions are executed by the processor, then cache coherence is maintained, but processor load and system complexity increase
Solution Approach 1:
The cache invalidation unit operates autonomously without requiring processor intervention. It independently monitors DMA operations, determines which cache entries need invalidation, and generates the appropriate invalidation requests. This self-service mechanism eliminates the need for processor-executed PUSH and INVALIDATE instructions, reducing processor load and preserving throughput.
Solution Approach 2:
The cache invalidation unit serves as an intermediary that handles the complexity of cache coherence management separately from the processor. It translates DMA write operations into cache invalidation actions without involving the processor, thereby maintaining coherence while preserving processor productivity.
Data Source
AI summary
The present application relates to a cache invalidation unit for a computing system having a processor unit, CPU, with a cache memory, a main memory and at least one an alternate bus master unit. The CPU, the main memory and the at least one an alternate bus master unit are coupled via an interconnect for data communications between them. The cache invalidation unit generates one or more invalidation requests to the cache memory in response to the alternate bus master unit writing data to the main memory. The cache invalidation unit comprises a page address generator unit to generate page addresses relating to at least one address range and an invalidation request generator unit to generate an invalidation request for each page address. The one or more generated invalidation requests are transmitted by the cache invalidation unit via to the cache memory of the CPU.