Hierarchical Cache Isolation for Trusted Core Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In trusted computing, existing technologies face challenges in effectively controlling access to isolated memory, where a trusted core can access it while preventing a normal core from doing so, without compromising security and efficiency.
Innovation Solution
A processor architecture with a trusted core and a normal core, featuring a hierarchical cache system that includes a shared last-level cache, where the normal core's memory access requests are evaluated to determine if they hit the isolated memory, and if so, the requests are rejected, with mechanisms to prevent illegal access and trigger interrupts as necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the normal core shares the last-level cache with the trusted core to improve memory access efficiency, then the productivity is improved, but the normal core may accidentally access the isolated memory, compromising security
Solution Approach 1:
The patent segments the memory space into isolated memory regions and non-isolated memory regions. The cache system is divided into a first cache (for non-isolated memory) and a second cache (for isolated memory). This segmentation ensures that the normal core can efficiently access non-isolated memory through the first cache while the isolated memory is protected in the separate second cache, preventing accidental access and maintaining both productivity and security.
2Reliability
If the hierarchical cache system checks every memory access request to determine if it hits the isolated memory to prevent unauthorized access, then the reliability is improved, but the processing time increases, reducing productivity
Solution Approach 1:
The patent implements preliminary action by pre-establishing a mapping relationship between virtual addresses and physical addresses, and pre-identifying which memory regions are isolated. When a memory access request occurs, the system quickly determines whether the requested address falls within the isolated memory range using the pre-computed mapping information, rather than checking every single access request from scratch. This reduces the overhead and maintains high productivity while ensuring reliable access control.
3Device complexity
If the system uses a shared last-level cache between normal core and trusted core to reduce hardware complexity, then the device complexity is reduced, but it becomes difficult to detect and prevent illegal access to isolated memory
Solution Approach 1:
The patent uses a tagging mechanism analogous to color changes to distinguish between different types of memory accesses. Each cache line is tagged with information indicating whether it belongs to isolated memory or non-isolated memory. This tagging system allows the cache system to maintain a unified structure (reducing complexity) while simultaneously enabling easy detection of illegal access attempts (improving detectability). When the normal core attempts to access isolated memory, the tag mismatch immediately detects the illegal access.
Data Source
AI summary
A processor with protection of an isolated memory and protection method for the isolated memory accessible only by a trusted core are shown. A processor has a trusted core with a right to access an isolated memory planned on a system memory, a normal core prohibited from accessing the isolated memory, and a last-level cache shared by the trusted core and the normal core. The in-core cache structure of the normal core and the last-level cache are included in a hierarchical cache system. In response to a memory access request issued by the normal core, the hierarchical cache system determines whether the memory access request hits the isolated memory and, if yes, the hierarchical cache system rejects the memory access request.