Multi-Core Cache Key Protection via Intel TSX
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Solution Overview
Problem
Current computer security systems face threats from system intrusions and physical attacks, particularly the cold boot attack, which compromise the security of private keys stored in memory, and existing solutions are inefficient due to limitations in register capacity and cache sharing in multi-core processors.
Innovation Solution
A key protection method that sets a symmetric master key in each core of a multi-core processor, uses Intel Transactional Synchronization Extensions (TSX) to dynamically record and abort memory accesses, and stores plaintext private keys and intermediate variables in the cache, ensuring secure storage and operation efficiency by preventing synchronization with physical memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the private key is stored in memory, then the cryptographic operations can be performed, but the system is vulnerable to system intrusions and physical attacks that directly access memory
Solution Approach 1:
The patent divides the multi-core processor into isolated core units, each with its own private cache memory. The private key is segmented and stored in the cache of a specific core rather than in shared system memory, preventing system-wide intrusions from accessing the key while maintaining cryptographic operation capability.
Solution Approach 2:
The patent introduces a cache memory as an intermediary between the processing core and the main memory. The private key is stored in the cache of a specific core, which acts as a protected intermediate storage layer that prevents direct access from other cores or system intrusions while enabling cryptographic operations.
2Reliability
If the private key is stored in a register, then the key security is improved, but the register capacity is limited and only supports symmetric cryptographic algorithms with limited key length
Solution Approach 1:
The patent transitions from the one-dimensional limitation of register capacity to the two-dimensional solution of using cache memory with sufficient capacity. The cache provides both the security of isolated storage and the capacity needed for public-key cryptographic algorithms with longer key lengths, resolving the trade-off between security and algorithm versatility.
3Reliability
If the key is stored in an on-chip cache of a multi-core processor, then the security against memory attacks is improved, but cache sharing among cores reduces processing efficiency
Solution Approach 1:
The patent segments the cache memory into private caches for each core, with the private key stored in the cache of a specific core. This segmentation prevents other cores from accessing the key while allowing the hosting core to perform cryptographic operations efficiently without cache sharing conflicts.
Solution Approach 2:
The patent applies local quality by giving each core its own private cache space for storing cryptographic keys and intermediate variables. This local isolation ensures that cryptographic operations in one core do not interfere with operations in other cores, maintaining high processor efficiency while ensuring key security.
4Reliability
If all cores are configured as no-fill mode to prevent cache sharing, then the private key security is maintained, but only one core can perform cryptographic operations at the same time
Solution Approach 1:
The patent segments the cache memory into private caches for each core, allowing multiple cores to operate concurrently with their own private key material. This eliminates the need for no-fill mode configuration while maintaining security, as each core's private cache is isolated from others.
Solution Approach 2:
The patent makes the cache system universal by allowing each core to use its own private cache for cryptographic operations independently. This enables multiple cores to perform cryptographic operations simultaneously without interfering with each other, while the same cache infrastructure provides security protection for all cores.
Data Source
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AI summary
An embodiment of the present disclosure provide a key protection method, via setting that each core of the multi-core process may have one symmetric master key, dynamically obtaining the plaintext private key of the asymmetric algorithm via a decryption operation and using the Intel TSX, it may be ensured that the private key and the intermediate variables used in the computation process may be stored in the cache occupied by the operation core only in terms of the hardware level, which may prevent the attackers from stealing the private key from the physical memory and ensure the security of the implementation of the public-key cryptographic algorithm in the computer system. Further, even the OS may be compromised and the attacker may directly read the memory storing the key, since the Intel TSX mechanism may ensure the atomicity of the memory operation, the attacker cannot obtain the plaintext private key. Further, in this scheme, while the physical attacks and system intrusions are resisted, the other cores of the multi-core processor may perform the cryptographic operation, which may enhance the operation efficiency.