Cache Latch Circuit Two-Dimensional Arrangement Data Line Loading
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing data output speed due to high loading on data lines and inverted data lines, which hinders the rapid development and amplification of signals necessary for efficient data transfer.
Innovation Solution
The semiconductor memory device incorporates a cache latch circuit with a two-dimensional arrangement of cache latches and local sense amplifiers, where even and odd cache latches share data lines and inverted data lines, and are strategically positioned to reduce wiring overlap with the local sense amplifier, thereby minimizing loading and enhancing signal development speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If cache latches are arranged in a two-dimensional configuration with even and odd cache latches sharing data lines and inverted data lines, then device area is reduced, but loading on data lines and inverted data lines increases
Solution Approach 1:
The patent applies two-dimensional arrangement of cache latches in row and column directions, allowing even and odd cache latches to share data lines and inverted data lines. This spatial reorganization reduces the overall device area while managing loading effects through strategic positioning of sense amplifiers.
Solution Approach 2:
Local sense amplifiers are introduced as intermediary components between cache latches and column selection sections. These sense amplifiers serve as buffers that reduce the loading effect on shared data lines and inverted data lines, enabling multiple cache latches to share lines without excessive loading while maintaining compact two-dimensional layout.
2Speed
If cache latches are positioned to reduce wiring overlap with local sense amplifier, then signal development speed is improved, but device layout complexity increases
Solution Approach 1:
The patent implements local optimization by strategically positioning even and odd cache latches to minimize wiring overlap with local sense amplifiers in specific regions. This local quality adjustment reduces capacitive coupling and interference, improving signal development speed without requiring complete redesign of the entire device layout.
Solution Approach 2:
The cache latch circuit is segmented into even cache latches and odd cache latches that can be independently positioned and optimized. This segmentation allows separate optimization of wiring paths for different latch groups, reducing overall layout complexity while improving signal development speed through minimized overlap with sense amplifiers.
Data Source
AI summary
A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.