Cache Latch Circuit Diagonal Layout for NAND Flash Defect Repair
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Solution Overview
Problem
NAND flash memory devices face challenges in efficiently reading and writing data due to the limitations of their page buffer operations, which can lead to defects and reduced defect repair efficiency as the density of memory devices increases, causing read errors and requiring complex column repair mechanisms.
Innovation Solution
The semiconductor memory device incorporates a cache latch circuit with a specific arrangement of cache latches and bit line select transistors, including a column-based single-direction diagonal layout for bit line contacts, to improve defect repair efficiency and reduce the likelihood of bit line shorts, while also optimizing the layout of sensing latches and column decoders to simplify wiring and reduce the number of column decoders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache latches are arranged in a conventional grid pattern to improve data exchange efficiency, then read/write speed is improved, but the risk of bit line shorts and defects increases
Solution Approach 1:
The patent applies asymmetry by arranging cache latches in a diagonal pattern rather than a conventional symmetric grid. Specifically, even cache latches are positioned at coordinates (2i, 2j) while odd cache latches are positioned at (2i+1, 2j+1), creating an asymmetric diagonal distribution that increases spacing between bit line contacts and reduces short circuit risk while maintaining data exchange efficiency
2Quantity of substance
If the density of memory devices is increased to improve storage capacity, then storage capacity is improved, but defect repair efficiency deteriorates
Solution Approach 1:
The patent segments the cache latch circuit into distinct even and odd latch groups with different diagonal arrangements. This segmentation allows independent optimization of each group's bit line routing, enabling defect repair in one segment without affecting the other, thus improving repair efficiency while maintaining high density
Solution Approach 2:
The patent introduces bit line select transistors as intermediary elements between the cache latches and bit lines. These transistors provide isolation and control, allowing defective latches to be selectively disconnected from bit lines, thereby enabling defect repair while maintaining high device density
3Reliability
If complex column repair mechanisms are added to handle read errors, then read error handling is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-arranging cache latches in diagonal patterns with built-in spacing that prevents bit line shorts. This preventive design reduces the occurrence of read errors caused by bit line defects, thereby reducing the need for complex column repair mechanisms while maintaining reliability
Data Source
AI summary
A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.