Page Buffer Cache Latch Overlap for Memory Read Performance
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Solution Overview
Problem
Current memory devices face inefficiencies in cache read operations due to sequential execution of data transfer and read operations, leading to prolonged read times and reduced performance.
Innovation Solution
The implementation of a page buffer system with a bit line sensing circuit, latch control circuit, main latch, and cache latch, where the cache latch operation overlaps with the bit line sensing operation, allowing simultaneous data transfer and read operations, thereby reducing read times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer operation and read operation are performed sequentially, then data integrity is ensured, but read time increases and performance decreases
Solution Approach 1:
The patent applies preliminary action by performing the data transfer operation from the main latch to the cache latch before the bit line sensing operation is completely finished. The latch control circuit initiates the cache latch operation in advance, allowing it to overlap with the bit line sensing operation. This preliminary initiation of the data transfer reduces the total read time by eliminating the sequential waiting period, while the latch control circuit ensures data integrity by managing the timing and connection between circuits.
Solution Approach 2:
The patent implements continuity of useful action by making the data transfer operation and bit line sensing operation overlap in time. Instead of completing one operation before starting the other, the latch control circuit enables both operations to proceed simultaneously during their overlapping period. This continuous overlapping execution eliminates idle time and maximizes the utilization of the memory system, improving read performance without compromising data integrity.
2Loss of time
If data transfer and read operations are overlapped, then read time is reduced, but circuit complexity increases
Solution Approach 1:
The latch control circuit serves as an intermediary that manages the overlapping operations between the bit line sensing circuit and the cache latch. It controls the timing and connection of these circuits, enabling the data transfer operation to overlap with the bit line sensing operation. This intermediary component coordinates the simultaneous operations, reducing read time while containing circuit complexity through centralized control logic rather than requiring complex interconnections between all components.
3Speed
If cache latch operation overlaps with bit line sensing operation, then data access speed improves, but control complexity increases
Solution Approach 1:
The latch control circuit implements feedback mechanisms to monitor the status of the bit line sensing circuit and the cache latch, and adjusts the timing and connection accordingly. This feedback control enables the cache latch operation to overlap with the bit line sensing operation while maintaining proper data integrity. The feedback ensures that data is transferred only when ready, improving data access speed while managing control complexity through status-driven coordination.
Data Source
AI summary
A page buffer includes a bit line sensing circuit, a latch, and a main latch for sensing and storing data from a memory cell. The bit line sensing circuit is coupled with the memory cell by a bit line and configured to perform a bit line sensing operation of sensing first data stored in the memory cell. The latch control circuit is coupled with the bit line sensing circuit. The main latch is coupled with the bit line sensing circuit through the latch control circuit and configured to perform a main latch operation of storing the sensed first data. The cache latch is coupled with the main latch and configured to perform a cache latch operation of storing second data stored in the main latch. Wherein a period of time of the cache latch operation overlaps with a period of time of the bit line sensing operation.