Cache Memory Leak Detection and Recovery in Storage Systems

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Solution Overview

Problem

In multi-controller storage systems with distributed cache memory, disruptive events like power loss or software/hardware exceptions can lead to partial cache slot allocations and orphaned slots, causing data unavailability and requiring costly manual recovery due to incomplete updates in cache metadata and track ID table metadata.

Innovation Solution

A memory management processor monitors processing threads with multiple cache states, updates data structures to indicate cache states, detects disruption events, and uses a recovery state machine to perform corrective actions, including scaling data structures based on the number of processing threads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If cache slot allocation is performed in distributed cache memory systems, then cache memory capacity and performance are improved, but disruptive events can cause partial allocations and orphaned slots leading to data unavailability

Engineering Contradiction:
Improvecache memory capacityVSAvoiddata availability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The system implements a feedback mechanism by continuously monitoring cache slot states through data structures that track allocation status. When disruptions occur, the monitoring system detects orphaned slots and triggers automated recovery processes that reallocate cache slots, ensuring data availability is maintained despite the increased cache capacity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies preliminary action by establishing monitoring and recovery mechanisms before disruptions occur. Data structures are pre-configured to track cache slot states, and recovery processes are prepared in advance to automatically detect and correct partial allocations, preventing data unavailability before it can impact system operation

Inventive Principle:
Principle #10Preliminary action

2Reliability

If manual recovery processes are implemented for cache memory leaks, then data loss can be prevented, but recovery costs and time are increased

Engineering Contradiction:
Improvedata loss preventionVSAvoidrecovery time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system implements self-service by enabling automated detection and recovery of cache memory leaks. The monitoring mechanism continuously tracks cache slot states and automatically triggers recovery processes when disruptions are detected, eliminating the need for manual intervention and significantly reducing recovery time while maintaining data loss prevention

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The feedback mechanism provides continuous monitoring of cache slot states and automatically initiates recovery actions when leaks are detected. This closed-loop system prevents data loss by immediately responding to disruptions without requiring manual recovery processes, thereby reducing both recovery time and operational costs

Inventive Principle:
Principle #23Feedback

3Difficulty of detecting and measuring

If data structures are updated to track cache states for each processing thread, then cache memory leak detection is improved, but system complexity is increased

Engineering Contradiction:
Improvecache leak detection capabilityVSAvoidsystem complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The system applies segmentation by creating separate data structures for each processing thread to track individual cache slot states. This modular approach enables precise detection of cache leaks in specific threads without requiring complex global analysis, improving detection capability while managing system complexity through structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements universality by designing a standardized data structure template that can be applied to all processing threads. This multi-functional approach allows the same monitoring mechanism to track cache states across multiple threads uniformly, improving leak detection capability without proportionally increasing system complexity through reuse of the same structural pattern

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of manufacture

If automated recovery processes are implemented, then manual recovery costs are reduced, but the risk of incorrect recovery actions increases

Engineering Contradiction:
Improverecovery costVSAvoidrecovery accuracy
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The feedback mechanism provides continuous verification of cache slot states during the recovery process. The monitoring system tracks allocation status and validates recovery actions, ensuring that automated processes correctly identify and fix cache leaks without introducing new errors, thereby maintaining recovery accuracy while reducing manual costs

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system applies preliminary action by establishing validation rules and recovery protocols before automated processes execute. These pre-configured guidelines ensure that recovery actions follow proven procedures, reducing the risk of incorrect actions while maintaining the cost benefits of automation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11080190B2Detecting and correcting cache memory leaks
Publication Date: 2021.08.03 EMC IP HLDG CO LLC
  • US11080190B2 patent drawing
  • US11080190B2 patent drawing
  • US11080190B2 patent drawing

AI summary

Embodiments of the present disclosure relate to an apparatus comprising a memory and at least one processor. The at least one processor is configured to monitor one or more processing threads of a storage device. Each of the one or more processing threads includes two or more cache states. The at least one processor also updates one or more data structures to indicate a subject cache state of each of the one or more processing threads and detect an event that disrupts at least one of the one or more processing threads. Further, the processor determines a cache state of the at least one of the one or more processing threads contemporaneous to the disruption event using the one or more data structures and performs a recovery process for the disrupted at least one of the one or more processing threads.