Cache Memory Supply Rail Switching for Leakage Power Reduction
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Solution Overview
Problem
Current power management systems face challenges in reducing leakage power in low power modes, particularly when transitioning from active modes to low power modes, as the higher supply voltage in turbo modes increases leakage power significantly, leading to inefficiencies in battery-powered devices.
Innovation Solution
A system that includes a multiplexer and controller to selectively couple different supply rails to the cache memory based on performance modes, and a trigger device to detect clock signal gating, switching the cache memory from a higher supply voltage to a lower one when in turbo mode to reduce leakage power, and back when returning to active mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the processor operates in turbo mode with higher supply voltage, then processing speed is improved, but leakage power increases significantly
Solution Approach 1:
The patent dynamically switches the cache memory supply voltage based on processor operating mode. A multiplexer selects between a first supply rail (higher voltage for turbo mode) and a second supply rail (lower voltage for low power mode), allowing the system to adapt the cache supply voltage to current operational requirements and minimize leakage power during idle periods
Solution Approach 2:
The patent changes the supply voltage parameter of the cache memory based on processor state. When the processor enters low power mode, the cache memory supply voltage is reduced from the higher turbo mode voltage to a lower idle mode voltage, directly addressing the leakage power issue while maintaining operational capability
2Loss of energy
If the cache memory is powered down to reduce leakage power, then energy consumption is reduced, but memory access latency increases
Solution Approach 1:
The patent applies different supply voltages to different operational states of the cache memory. Rather than completely powering down the cache, it maintains a lower but non-zero supply voltage during idle modes, preserving basic functionality and reducing wake-up latency while still achieving significant leakage power reduction compared to full power operation
Solution Approach 2:
The system prepares the cache memory for quick recovery by maintaining it in a low-power state rather than fully powered down. The multiplexer and controller are pre-configured to rapidly switch supply rails when the processor exits idle mode, minimizing the transition time and ensuring fast memory access is restored quickly
3Loss of energy
If the supply voltage to cache memory is reduced in low power mode, then leakage power is reduced, but memory access speed decreases
Solution Approach 1:
The patent implements dynamic supply voltage scaling for the cache memory based on processor activity. The multiplexer switches between supply rails controlled by a trigger device that detects processor state, allowing the cache to operate at higher speeds during turbo mode and lower speeds during idle mode, accepting reduced memory access speed as a necessary trade-off for significant leakage power reduction
Data Source
AI summary
In some aspects, a method for managing leakage power includes coupling a first supply rail to a cache memory if a processor is in a first performance mode, wherein the processor accesses the cache memory, and coupling a second supply rail to the cache memory if the processor is in a second performance mode. The method also includes detecting gating of a clock signal to the cache memory or the processor, and, upon detecting gating of the clock signal, switching the cache memory from the second supply rail to the first supply rail if the cache memory is currently coupled to the second supply rail.