In-Core Cache Level Designation for Write-Back and Invalidation
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Solution Overview
Problem
Traditional writing-back and invalidation techniques for cached data in hierarchical cache systems are not suitable for all applications, particularly in multi-core processors where they can affect the execution speed of other cores and lead to redundant operations.
Innovation Solution
The proposed solution involves designating a specific level cache within the current core as the target for writing-back and invalidation, allowing for focused operations that do not affect other cores, thereby avoiding redundant writing-back and invalidation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional writing-back and invalidation techniques are used in hierarchical cache systems, then cache data consistency is maintained, but the execution speed of other cores is affected and redundant operations occur
Solution Approach 1:
The patent segments the cache invalidation operation by introducing a level-designation mechanism that allows selective invalidation of cache lines at specific hierarchy levels (L1, L2, or both) within a core. This segmentation enables targeted operations that do not affect other cores, resolving the contradiction between maintaining data consistency and preserving core execution speed.
Solution Approach 2:
The patent applies local quality by allowing each core to designate its own specific cache level (L1 only, L2 only, or both) for writing-back and invalidation operations. This localized approach ensures that only the designated core's designated cache level is affected, preventing interference with other cores' execution while maintaining necessary data consistency.
2Reliability
If traditional writing-back and invalidation techniques are used, then cache coherence is ensured, but redundant writing-back and invalidation operations occur
Solution Approach 1:
The patent segments the cache coherence maintenance operation by introducing level-specific designation. Each core can independently designate which cache level(s) it needs to perform writing-back and invalidation on. This segmentation prevents redundant operations by ensuring that only the necessary cache levels are processed, avoiding unnecessary operations in other cores.
Solution Approach 2:
The patent introduces dynamic configuration through the level-designation request mechanism, where each core can dynamically specify its preferred cache level for operations. This dynamic approach allows the system to adapt to different operational scenarios and avoid redundant writing-back and invalidation operations by processing only what is currently needed.
3Reliability
If all cache levels are invalidated simultaneously, then cache consistency is maintained, but system performance is reduced due to interference between cores
Solution Approach 1:
The patent segments the cache invalidation process by allowing individual cores to designate specific cache levels (L1, L2, or both) for their operations. This segmentation isolates operations to specific levels and cores, preventing system-wide interference while maintaining necessary cache consistency at the designated levels.
Solution Approach 2:
The patent applies local quality by enabling each core to select its own designated cache level(s) for writing-back and invalidation. This localized approach ensures that performance-critical operations are confined to specific levels and cores, maintaining cache consistency where needed without degrading overall system performance.
Data Source
AI summary
A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.