Dynamic Cache Line Allocation for Real-Time Latency
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Solution Overview
Problem
System-on-a-chip (SoC) cache memories face challenges in efficiently managing cache allocation for low-latency memory transactions, particularly in handling real-time transactions and preventing cache misses that can lead to system failures due to high latency and competition for memory access.
Innovation Solution
A cache controller circuit configures a portion of the cache memory as directly-addressable RAM, prioritizing real-time transactions and allocating cache lines to reduce latency, while also distributing cache misses across a buffer to maintain consistent access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to store local copies of frequently accessed information, then access speed is improved, but memory allocation flexibility deteriorates
Solution Approach 1:
The patent implements dynamic allocation of cache lines between cache operations and directly-addressable RAM based on real-time transaction requirements. The cache controller can convert cache lines to directly-addressable RAM and back, allowing the memory allocation to adapt dynamically between cache mode (for speed) and direct address mode (for flexibility), resolving the contradiction between access speed and allocation flexibility.
2Reliability
If cache lines are allocated for caching operations, then cache hit rate is improved, but availability for real-time transactions deteriorates
Solution Approach 1:
The patent segments the cache memory into multiple cache lines that can be independently allocated for caching operations or converted to directly-addressable RAM for real-time transactions. This segmentation allows the system to maintain high cache hit rates for cached data while simultaneously providing dedicated memory space for real-time transactions, resolving the contradiction between cache effectiveness and real-time availability.
3Loss of time
If cache memory is used to reduce access delays, then transaction latency is improved, but memory access competition worsens
Solution Approach 1:
The patent extracts certain cache lines from the cache memory pool and converts them to directly-addressable RAM that is exclusively allocated for real-time transactions. This extraction removes the competition for these specific memory lines between cache operations and real-time transactions, ensuring that real-time transactions have dedicated access paths with guaranteed low latency, while the remaining cache lines continue to provide caching benefits for other operations.
Data Source
AI summary
An apparatus includes a cache controller circuit and a cache memory circuit that further includes cache memory having a plurality of cache lines. The cache controller circuit may be configured to receive a request to reallocate a portion of the cache memory circuit that is currently in use. This request may identify an address region corresponding to one or more of the cache lines. The cache controller circuit may be further configured, in response to the request, to convert the one or more cache lines to directly-addressable, random-access memory (RAM) by excluding the one or more cache lines from cache operations.