Cache Line Allocation for 3D Shader Memory Access
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Solution Overview
Problem
The existing cache architecture is inadequate for three-dimensional graphic shader applications, as it cannot store the entire instruction group in one operation, leading to repeated reads and writes from system memory, which reduces efficiency and increases access time.
Innovation Solution
A cache line allocation method that locks whole cache lines if the instruction size is less than or equal to the cache size, locks a first number of cache lines if the size difference is within a threshold, and locks a second number of cache lines if the size difference exceeds the threshold, optimizing cache utilization and reducing system memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cache size is increased to store the entire instruction group, then the cache hit rate improves, but the cache capacity and system complexity increase
Solution Approach 1:
The patent segments the instruction group into multiple cache lines, each storing a portion of the instructions. Instead of requiring a single large cache to hold all instructions, the system divides the instruction stream into manageable chunks that fit within the limited cache capacity, allowing multiple instruction groups to be managed across different cache lines.
Solution Approach 2:
The patent implements preliminary locking of cache lines before they are fully written. When a cache line is locked, it prevents subsequent overwriting operations, ensuring that partially written instruction groups are preserved. This preliminary locking action occurs before the cache line is completely filled, allowing the system to maintain instruction integrity without requiring the full instruction group to fit in cache.
2Reliability
If repeated reads and writes from system memory are performed to load instruction groups, then the cache can be filled with instructions, but the system access time and memory bandwidth consumption increase
Solution Approach 1:
The patent performs preliminary locking of cache lines during the write operation before the instruction group is fully loaded. This ensures that once a cache line is locked, it is protected from subsequent overwrites, allowing the system to minimize repeated reads from memory by preserving partially loaded instructions that may still be useful for subsequent processing.
Solution Approach 2:
The patent converts the harmful effect of incomplete instruction loading into a beneficial outcome by locking cache lines that contain partial instructions. Instead of discarding incomplete instruction groups as failures, the system locks these partial cache lines and uses them as-is, reducing the frequency of complete reloads from system memory and thereby reducing access time.
3Reliability
If cache lines are locked to prevent overwriting, then instruction integrity is maintained, but the cache utilization and writing flexibility decrease
Solution Approach 1:
The patent segments the cache into multiple independent cache lines, each of which can be locked independently. This segmentation allows the system to lock only the necessary portion of the cache that contains the current instruction group, rather than locking the entire cache. Consequently, other unlocked cache lines remain available for new instruction groups, maintaining high cache utilization while preserving instruction integrity in locked regions.
Data Source
AI summary
A cache line allocation method, wherein the cache is coupled to a graphic processing unit and the cache comprising a plurality of cache lines, each cache line stores one of a plurality of instructions the method comprising the steps of: putting the plurality of instructions in whole cache lines; locking the whole cache lines if an instruction size is less than a cache size; locking a first number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is less than or equal to a threshold; and locking a second number of cache lines when the instruction size is larger than the cache size and a difference between the instruction size and the cache size is large than the threshold; wherein the first number is greater than the second number.