Obscuring Memory Access Patterns via Cache Line Attributes
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Solution Overview
Problem
Processor-based systems face information leakage issues due to memory access patterns, where a 'spy' thread can observe and infer sensitive information from a 'target' thread's cache access patterns, especially when sharing a cache memory, leading to potential security breaches.
Innovation Solution
Implementing memory attributes associated with cache lines, such as attribute bits, to control and manage access, with instructions like LOAD_SET, LOAD_CHECK, and STORE_SET/STORE_CHECK, which allow a thread to register handlers for Memory Line Invalidate scenarios, obscuring access patterns by reloading critical memory locations in arbitrary orders and handling context switches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple threads share a cache memory to improve processor utilization, then system productivity increases, but information leakage occurs through observable memory access patterns
Solution Approach 1:
The patent introduces cache line attributes as an intermediary mechanism between threads and cache memory. These attributes act as mediators that prevent direct observation of access patterns by spy threads, while still allowing legitimate cache sharing for productivity improvement. The attributes serve as a protective layer that enables multi-threaded execution without information leakage.
2Speed
If cache lines are shared between threads to reduce memory access time, then speed improves, but security deteriorates due to side-channel attacks
Solution Approach 1:
The patent applies local quality by assigning specific attributes to individual cache lines rather than uniformly treating all cache memory. Each cache line can have its own access pattern obscuration attributes, allowing security-sensitive data to be protected while other data maintains normal cache sharing performance. This localized approach preserves speed for non-sensitive operations while providing security where needed.
3Reliability
If memory access patterns are obscured to prevent information leakage, then security improves, but cache performance deteriorates due to additional access control overhead
Solution Approach 1:
The patent implements preliminary action by pre-configuring cache line attributes and access patterns before actual data access occurs. The system establishes security policies and attribute settings in advance, so that during normal operation, the obscured access patterns are already in place without adding real-time overhead. This preparatory approach ensures security without degrading cache performance during critical data access operations.
Data Source
AI summary
For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache.