Cache-Line Copy-on-Write for Large Memory Page Overhead
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Solution Overview
Problem
Copy-on-write mechanisms incur overhead due to write protection and have a coarse granularity of memory page copying, which is inefficient for large memory pages, especially in virtual machine applications where pages can be 2 MB or 1 GB in size.
Innovation Solution
Implementing copy-on-write at the granularity of cache lines instead of entire pages, using a coherence interconnect and cache coherence protocol to manage shared memory pages, allowing for reduced overhead and efficient data duplication only when necessary, without requiring changes to the hypervisor or operating system kernel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If copy-on-write is implemented at memory page granularity, then sharing benefits are maintained, but copying overhead increases significantly for large memory pages
Solution Approach 1:
The patent divides the memory page into smaller cache line units (e.g., 64-byte units) and implements copy-on-write at this finer granularity. Instead of copying entire large pages (2MB or 1GB), only the specific cache lines that are modified are copied, dramatically reducing the copying overhead while maintaining the sharing benefits for unchanged portions.
2Reliability
If write protection mechanisms are used to detect memory page modifications, then copy-on-write functionality is enabled, but overhead for the affected process increases
Solution Approach 1:
The patent segments the write protection mechanism to operate at cache line granularity rather than page granularity. This allows more precise tracking of modifications, enabling the system to detect changes and trigger copy-on-write only for the specific cache lines that are modified, rather than requiring protection and potential copying of entire large pages.
Solution Approach 2:
The patent replaces the traditional page-level write protection mechanism with a cache-coherence-based detection mechanism. Instead of relying on OS-level page fault handling and write protection bits, the system uses hardware cache coherence protocols to detect modifications, reducing the overhead on affected processes while maintaining reliable detection.
3Reliability
If entire memory pages are copied when modification is detected, then data integrity is maintained, but memory consumption increases for large pages
Solution Approach 1:
The patent implements segmentation of the copying operation at cache line granularity. When a modification is detected in a specific cache line, only that cache line (or the containing small unit) is copied to a new location, rather than copying the entire large memory page. This maintains data integrity for the modified portion while dramatically reducing memory consumption for the copy operation.
Data Source
AI summary
A method of performing a copy-on-write on a shared memory page is carried out by a device communicating with a processor via a coherence interconnect. The method includes: adding a page table entry so that a request to read a first cache line of the shared memory page includes a cache-line address of the shared memory page and a request to write to a second cache line of the shared memory page includes a cache-line address of a new memory page; in response to the request to write to the second cache line, storing new data of the second cache line in a second memory and associating the second cache-line address with the new data stored in the second memory; and in response to a request to read the second cache line, reading the new data of the second cache line from the second memory.