Cache Line De-duplication via Hardware Pattern Detection
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Solution Overview
Problem
Existing methods for detecting and managing duplicated cache lines in memory are inefficient, often relying on software scans which are costly and resource-intensive, whereas hardware detection offers a more economical and efficient approach.
Innovation Solution
Implementing a system that detects cache line data patterns using digital logic gates and hardware-trained patterns, building a link-list between multiple physical addresses and their common data values to de-duplicate cache lines, utilizing a cache line filter table and overflow table to manage duplicate content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software is used to scan memory and detect duplicated cache lines, then duplication detection can be achieved, but the cost is very expensive and resource-intensive
Solution Approach 1:
The patent replaces software-based duplication detection with hardware-based detection using digital logic gates (XOR, AND, OR gates) that operate in parallel to compare cache line data patterns. This substitution of mechanical/software computation with hardware logic circuits dramatically reduces computational cost and energy consumption while maintaining detection accuracy.
Solution Approach 2:
The patent creates hardware copies of cache line data patterns through parallel comparison circuits that simultaneously check multiple cache lines against each other. These hardware copies enable rapid duplication detection without requiring sequential software processing, reducing the computational burden while achieving the same detection function.
2Productivity
If hardware is used to detect data patterns in memory, then detection efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory system into multiple cache sets, each with its own dedicated comparison circuits. This segmentation allows parallel processing of duplication detection across different cache sets, improving overall detection efficiency while managing hardware complexity by localizing the circuitry to specific cache regions rather than requiring a monolithic complex circuit.
Solution Approach 2:
The patent designs the hardware detection circuitry to perform multiple functions: comparing cache line data patterns, generating duplication detection signals, and interfacing with cache control logic. This multi-functionality reduces the need for separate dedicated circuits for each task, thereby improving detection efficiency without proportionally increasing overall device complexity.
3Quantity of substance
If duplicate cache lines are stored in memory, then memory capacity is充分利用, but memory usage efficiency decreases due to redundancy
Solution Approach 1:
The patent implements a self-service mechanism where the hardware detection circuit automatically identifies duplicate cache lines and generates signals to prevent their storage. The system serves itself by using the stored data patterns to detect and eliminate redundancies without requiring external software intervention, thereby reducing memory usage inefficiency while maintaining full capacity utilization.
Solution Approach 2:
The patent discards redundant duplicate cache line data by preventing their storage in memory through hardware-generated invalidation signals. When duplicates are detected, the system recovers memory space by ensuring only unique data patterns are stored, thereby eliminating wasteful redundancy while maintaining optimal memory capacity utilization for actual unique data.
Data Source
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AI summary
Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string.