Delayed Snoop Cache-Line Handling for False Sharing Bottlenecks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-core coherent systems, maintaining cache coherency and reducing CPU stall overhead while maximizing memory throughput is challenging due to varying cache structures and access patterns among different processor components, leading to bottlenecks in data consistency and shared memory access.
Innovation Solution
A method is introduced where data blocks are stored in a cache line, with each processor maintaining a local copy and executing child processes to generate output data, allowing write-through operations while transmitting invalidate requests to other processors to manage cache coherency and reduce stall overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional cache coherency protocols are used to maintain data consistency across multiple processors, then data coherency is guaranteed, but CPU stall overhead increases and memory throughput decreases due to serial snoop and evict operations
Solution Approach 1:
The patent segments the cache line into multiple data blocks, each associated with a specific processor. This segmentation allows parallel processing of different data blocks by different processors without requiring serial snoop and evict operations, thereby reducing CPU stall overhead while maintaining data coherency through targeted invalidation of only the affected data block in other processors' caches.
Solution Approach 2:
The patent implements local quality by allowing each processor to have exclusive write access to its assigned data block within a cache line while maintaining read access to other data blocks. This local quality approach enables parallel writes to different data blocks without requiring global cache invalidation, reducing CPU stall overhead while preserving data coherency through selective invalidation.
2Reliability
If serial snoop and evict operations are performed to maintain cache coherency in false sharing scenarios, then data consistency is ensured, but memory throughput decreases due to bottleneck in the interconnect
Solution Approach 1:
The patent segments the cache line into multiple data blocks with each block independently trackable by the interconnect. This segmentation allows the interconnect to handle invalidation requests for specific data blocks in parallel rather than serially invalidating entire cache lines, thereby increasing memory throughput while ensuring data consistency through targeted invalidation of only the modified data block.
Solution Approach 2:
The patent implements preliminary action by pre-segmenting cache lines into data blocks and pre-establishing ownership relationships between processors and data blocks before false sharing occurs. This preliminary segmentation enables the interconnect to efficiently handle invalidation requests by directly targeting specific data blocks rather than performing serial snoop operations across all processors, thereby increasing memory throughput while maintaining data consistency.
3Reliability
If cache lines are invalidated across all processors to maintain coherency, then data coherency is maintained, but CPU stall overhead increases and processing parallelism is reduced
Solution Approach 1:
The patent segments cache lines into independent data blocks that can be individually invalidated. This segmentation allows processors to continue processing other data blocks in parallel while one data block is being invalidated, thereby maintaining data coherency for the modified block while preserving processing parallelism for other blocks, reducing CPU stall overhead compared to full cache line invalidation.
Solution Approach 2:
The patent applies partial action by invalidating only the specific data block that requires coherency maintenance rather than invalidating the entire cache line. This partial invalidation approach maintains data coherency for the affected block while allowing other processors to continue accessing and processing other data blocks in the same cache line without interruption, thereby preserving processing parallelism and reducing CPU stall overhead.
Data Source
AI summary
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.