Cache Line Compression With Low-Latency Dictionary Decompression
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Solution Overview
Problem
The growing gap between on-chip compute resources and external memory system bandwidth is not adequately addressed by existing cache compression methods, which offer power and performance benefits but are limited by reasonable compression rates and increased decompression latency.
Innovation Solution
A method and apparatus for compressing and decompressing data blocks, specifically cache lines, using fixed-size symbols and dictionary entries to achieve efficient compression and low-latency decompression, allowing for a 2:1 compression ratio with minimal latency, and potentially higher ratios like 4:1 or 8:1, by using a symbol portion and data portion structure within the cache architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cache compression is implemented, then memory bandwidth requirements are reduced and effective cache capacity is increased, but decompression latency increases and die area for compression logic increases
Solution Approach 1:
The patent divides the cache line into multiple words (e.g., 4 words of 16 bits each) and processes them independently through parallel decompression logic. Each word has dedicated decompression circuits that can operate simultaneously, reducing overall decompression latency while maintaining compression benefits for the entire cache line.
Solution Approach 2:
The patent implements dynamic decompression where the compression ratio and decompression path are determined based on the actual data patterns. The system can adaptively select between different decompression strategies (e.g., full decompression vs. partial decompression) based on workload characteristics, optimizing the balance between latency and bandwidth savings.
2Quantity of substance
If cache compression is implemented, then memory bandwidth requirements are reduced, but die area for compression logic increases
Solution Approach 1:
The patent combines the compression and decompression logic into shared circuitry that serves both functions. The same logical units used for compression during write operations are reused for decompression during read operations, eliminating the need for completely separate logic blocks and reducing overall die area.
Solution Approach 2:
The compression logic is designed to be multi-functional, serving both as a compression engine during cache writes and as a decompression engine during cache reads. This universal logic reduces the total die area required compared to having dedicated separate compression and decompression units.
3Quantity of substance
If higher compression ratios are achieved, then memory bandwidth savings increase, but decompression complexity and latency increase
Solution Approach 1:
The patent segments the decompression process into independent word-level operations rather than processing the entire cache line as a single unit. This segmentation allows parallel processing of multiple words simultaneously, reducing decompression complexity and latency while maintaining high compression ratios through efficient use of dictionary entries and literal values.
Data Source
AI summary
A compression technique includes storing respective fixed-size symbols for each of a plurality of words in a data block, e.g., a cache line, into a symbol portion of a compressed data block, e.g., a compressed cache line, where each of the symbols provides information about a corresponding one of the words in the data block. Up to a first plurality of data segments are stored in a data portion of the compressed data block, each data segment corresponds to a unique one of the symbols in the compressed data block and a unique one of the words in the cache line. Up to a second plurality of dictionary entries are stored in the data portion of the compressed cache line. The dictionary entries can correspond to multiple ones of the symbols.