Cache Line ECC Handling for Partial Writes and Memory Scrubbing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In data processing systems, partial writes to memory blocks require reading all data values to calculate an error code, leading to significant time and energy overhead, especially in cache memories where this can increase latency and complexity.
Innovation Solution
An error code generating circuitry that marks the error code as invalid for partially written data blocks, allowing the system to forego error code protection for those blocks, thereby reducing overhead, while maintaining strong error code protection statistically across the memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error code generation requires all data values to be available, then error detection reliability is improved, but write operation time and energy overhead increases significantly
Solution Approach 1:
The patent applies partial action by generating error codes only for the portion of data that has been written so far, rather than waiting for the complete data block. The error code is updated incrementally as each byte is written, allowing the write operation to proceed without waiting for all data values to be available, thus reducing write latency while maintaining error detection capability for the written portion.
Solution Approach 2:
The patent uses preliminary action by pre-calculating and storing error codes for individual bytes before they are combined into the complete data block. When a partial write occurs, the error code for the written portion can be immediately generated using pre-computed values, eliminating the need to wait for all data to arrive before error detection can begin.
2Reliability
If all data values must be read to compute error code for partial writes, then error detection accuracy is maintained, but energy consumption and system complexity increase
Solution Approach 1:
The system performs partial error code generation by computing error codes only for the bytes that have been written, rather than reading and processing all bytes in the data block. This reduces energy consumption proportionally to the fraction of data written, while still providing error detection for the valid written portion.
Solution Approach 2:
The patent extracts only the necessary portion of data (the written bytes) for error code computation, rather than requiring all data values. The error code generation is decoupled from the complete data block and applied selectively to the subset of data that is actually present and valid.
3Reliability
If error code protection is maintained for partially written blocks, then data integrity is improved, but write operation complexity and latency increase
Solution Approach 1:
The patent segments the error code generation process into independent per-byte operations. Each byte contributes independently to the error code through XOR accumulation, allowing the error code to be updated incrementally with each write operation without requiring complex coordination or waiting for complete data blocks.
Solution Approach 2:
The system accepts partial error code protection for partially written blocks, generating error codes only for the written portion rather than requiring complete data blocks. This reduces write operation complexity and latency while maintaining adequate data integrity protection for the valid data present.
Data Source
AI summary
A memory 10 stores a data block comprising a plurality of data values DV. An error code, such as an error correction code ECC, is associated with the memory and has a value dependent upon the plurality of data values which form the data block stored within the memory. If a partial write is performed on a data block, then the ECC information becomes invalid and is marked with an ECC_invalid flag. The intent is avoiding the need to read all data values to compute the ECC and thus save time and energy. The memory may be a cache line 28 within a level 1 cache memory 10. Memory scrub control circuitry 38 performs periodic memory scrub operations which trigger flushing of partially written cache lines back to main memory.